From f308f9696faa5dc3cd34b9acc2ce8de422630c86 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 12 Oct 2015 20:54:31 -0700 Subject: rvc 1.8 candidate --- opcodes-rvc | 36 ++++++++++++++++++------------------ opcodes-rvc-pseudo | 6 +++--- 2 files changed, 21 insertions(+), 21 deletions(-) diff --git a/opcodes-rvc b/opcodes-rvc index 39b960e..82831b1 100644 --- a/opcodes-rvc +++ b/opcodes-rvc @@ -10,24 +10,24 @@ c.sw 1..0=0 15..13=6 12=ignore 11..2=ignore c.fsw 1..0=0 15..13=7 12=ignore 11..2=ignore # c.sd for RV64 # C1 encoding space -c.srli 1..0=1 15..13=0 12=ignore 11..10=0 9..2=ignore -c.srai 1..0=1 15..13=0 12=ignore 11..10=1 9..2=ignore -c.andi 1..0=1 15..13=0 12=ignore 11..10=2 9..2=ignore -c.addw 1..0=1 15..13=0 12=0 11..10=3 9..7=ignore 6..5=0 4..2=ignore -c.sll 1..0=1 15..13=0 12=0 11..10=3 9..7=ignore 6..5=1 4..2=ignore -c.subw 1..0=1 15..13=0 12=0 11..10=3 9..7=ignore 6..5=2 4..2=ignore -c.sub 1..0=1 15..13=0 12=0 11..10=3 9..7=ignore 6..5=3 4..2=ignore -c.xor 1..0=1 15..13=0 12=1 11..10=3 9..7=ignore 6..5=0 4..2=ignore -c.srl 1..0=1 15..13=0 12=1 11..10=3 9..7=ignore 6..5=1 4..2=ignore -c.or 1..0=1 15..13=0 12=1 11..10=3 9..7=ignore 6..5=2 4..2=ignore -c.and 1..0=1 15..13=0 12=1 11..10=3 9..7=ignore 6..5=3 4..2=ignore -c.j 1..0=1 15..13=1 12=ignore 11..2=ignore -c.beqz 1..0=1 15..13=2 12=ignore 11..2=ignore -c.bnez 1..0=1 15..13=3 12=ignore 11..2=ignore -c.addi 1..0=1 15..13=4 12=ignore 11..2=ignore -c.jal 1..0=1 15..13=5 12=ignore 11..2=ignore # c.addiw for RV64 -c.li 1..0=1 15..13=6 12=ignore 11..2=ignore -c.lui 1..0=1 15..13=7 12=ignore 11..2=ignore # c.addi16sp when rd=2 +c.addi 1..0=1 15..13=0 12=ignore 11..2=ignore +c.jal 1..0=1 15..13=1 12=ignore 11..2=ignore # c.addiw for RV64 +c.li 1..0=1 15..13=2 12=ignore 11..2=ignore +c.lui 1..0=1 15..13=3 12=ignore 11..2=ignore # c.addi16sp when rd=2 +c.srli 1..0=1 15..13=4 12=ignore 11..10=0 9..2=ignore +c.srai 1..0=1 15..13=4 12=ignore 11..10=1 9..2=ignore +c.andi 1..0=1 15..13=4 12=ignore 11..10=2 9..2=ignore +c.addw 1..0=1 15..13=4 12=0 11..10=3 9..7=ignore 6..5=0 4..2=ignore +c.sll 1..0=1 15..13=4 12=0 11..10=3 9..7=ignore 6..5=1 4..2=ignore +c.subw 1..0=1 15..13=4 12=0 11..10=3 9..7=ignore 6..5=2 4..2=ignore +c.sub 1..0=1 15..13=4 12=0 11..10=3 9..7=ignore 6..5=3 4..2=ignore +c.xor 1..0=1 15..13=4 12=1 11..10=3 9..7=ignore 6..5=0 4..2=ignore +c.srl 1..0=1 15..13=4 12=1 11..10=3 9..7=ignore 6..5=1 4..2=ignore +c.or 1..0=1 15..13=4 12=1 11..10=3 9..7=ignore 6..5=2 4..2=ignore +c.and 1..0=1 15..13=4 12=1 11..10=3 9..7=ignore 6..5=3 4..2=ignore +c.j 1..0=1 15..13=5 12=ignore 11..2=ignore +c.beqz 1..0=1 15..13=6 12=ignore 11..2=ignore +c.bnez 1..0=1 15..13=7 12=ignore 11..2=ignore # C2 encoding space c.slli 1..0=2 15..13=0 12=ignore 11..2=ignore diff --git a/opcodes-rvc-pseudo b/opcodes-rvc-pseudo index 43c6199..2f60cc6 100644 --- a/opcodes-rvc-pseudo +++ b/opcodes-rvc-pseudo @@ -1,8 +1,8 @@ # these aren't really pseudo-ops, but they overlay other encodings, # so they are here to prevent parse-opcodes from barfing -@c.nop 1..0=1 15..13=4 12=0 11..7=0 6..2=0 -@c.addi16sp 1..0=1 15..13=7 12=ignore 11..7=2 6..2=ignore +@c.nop 1..0=1 15..13=0 12=0 11..7=0 6..2=0 +@c.addi16sp 1..0=1 15..13=3 12=ignore 11..7=2 6..2=ignore @c.jr 1..0=2 15..13=4 12=0 11..7=ignore 6..2=0 @c.jalr 1..0=2 15..13=4 12=1 11..7=ignore 6..2=0 @c.ebreak 1..0=2 15..13=4 12=1 11..7=0 6..2=0 @@ -10,6 +10,6 @@ # RV64C @c.ld 1..0=0 15..13=3 12=ignore 11..2=ignore # c.flw for RV32 @c.sd 1..0=0 15..13=7 12=ignore 11..2=ignore # c.fsw for RV32 -@c.addiw 1..0=1 15..13=5 12=ignore 11..2=ignore # c.jal for RV32 +@c.addiw 1..0=1 15..13=1 12=ignore 11..2=ignore # c.jal for RV32 @c.ldsp 1..0=2 15..13=3 12=ignore 11..2=ignore # c.flwsp for RV32 @c.sdsp 1..0=2 15..13=7 12=ignore 11..2=ignore # c.fswsp for RV32 -- cgit v1.2.3