From f1f72abca9f7511990c476d326c864c96a758732 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU>
Date: Sun, 19 Jun 2011 19:18:54 -0700
Subject: [riscv-isa-run] code cleanup; added README

---
 Makefile       | 22 ++++++++++++++++++++++
 inst.v         |  1 +
 parse-opcodes  |  7 ++++---
 update-opcodes |  6 ------
 4 files changed, 27 insertions(+), 9 deletions(-)
 create mode 100755 Makefile
 delete mode 100755 update-opcodes

diff --git a/Makefile b/Makefile
new file mode 100755
index 0000000..9029847
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,22 @@
+ISASIM_H := ../riscv-isa-run/riscv/opcodes.h
+PK_H := ../pk/pk/riscv-opc.h
+XCC_H := ../xcc/src/include/opcode/mips-riscv-opc.h
+
+install: $(ISASIM_H) $(PK_H) $(XCC_H) inst.v instr-table.tex
+
+$(ISASIM_H): opcodes parse-opcodes
+	./parse-opcodes -isasim < $< > $@
+
+$(PK_H): opcodes parse-opcodes
+	./parse-opcodes -disasm < $< > $@
+
+$(XCC_H): opcodes parse-opcodes
+	./parse-opcodes -disasm < $< > $@
+
+inst.v: opcodes parse-opcodes
+	./parse-opcodes -verilog < $< > $@
+
+instr-table.tex: opcodes parse-opcodes
+	./parse-opcodes -tex < $< > $@
+
+.PHONY : install
diff --git a/inst.v b/inst.v
index 9a644b3..fde166a 100644
--- a/inst.v
+++ b/inst.v
@@ -1,3 +1,4 @@
+/* Automatically generated by parse-opcodes */
 `define J          32'b?????????????????????????_1100111
 `define JAL        32'b?????????????????????????_1101111
 `define JALR_C     32'b?????_?????_????????????_000_1101011
diff --git a/parse-opcodes b/parse-opcodes
index 707947e..26b8779 100755
--- a/parse-opcodes
+++ b/parse-opcodes
@@ -85,7 +85,7 @@ def make_disasm_table(match,mask):
     print '#define MATCH_%s %s' % (name2, hex(match))
     print '#define  MASK_%s %s' % (name2, hex(mask[name]))
 
-def make_switch(match, mask):
+def make_isasim(match, mask):
   for name in match.iterkeys():
     name2 = name.replace('.','_')
     print 'DECLARE_INSN(%s, 0x%x, 0x%x)' % (name2, match[name], mask[name])
@@ -683,6 +683,7 @@ def print_verilog_r_type(name,match,arguments):
   )
 
 def make_verilog():
+  print '/* Automatically generated by parse-opcodes */'
   for name in namelist:
     if types[name] == 0:
       print_verilog_unimp_type(name,match[name],arguments[name])
@@ -784,7 +785,7 @@ elif sys.argv[1] == '-verilog':
   make_verilog()
 elif sys.argv[1] == '-disasm':
   make_disasm_table(match,mask)
-elif sys.argv[1] == '-switch':
-  make_switch(match,mask)
+elif sys.argv[1] == '-isasim':
+  make_isasim(match,mask)
 else:
   assert 0
diff --git a/update-opcodes b/update-opcodes
deleted file mode 100755
index 5df9fa3..0000000
--- a/update-opcodes
+++ /dev/null
@@ -1,6 +0,0 @@
-#!/bin/bash
-./parse-opcodes -tex < opcodes > instr-table.tex
-./parse-opcodes -verilog < opcodes > inst.v
-./parse-opcodes -disasm < opcodes > ../xcc/src/include/opcode/mips-riscv-opc.h
-./parse-opcodes -disasm < opcodes > ../pk/pk/riscv-opc.h
-./parse-opcodes -switch < opcodes > ../sim/riscv/opcodes.h
-- 
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