From ad9480bf5347c4371f4c33b5b8204833e6e34357 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 15 Oct 2010 17:51:37 -0700 Subject: [pk, sim] added FPU emulation support to proxy kernel --- inst.v | 2 +- instr-table.tex | 2 +- update-opcodes | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/inst.v b/inst.v index 493516e..dfd8e44 100644 --- a/inst.v +++ b/inst.v @@ -139,7 +139,7 @@ `define MFFH_D 32'b1101010_?????_00000_1101011010_????? `define MTF_S 32'b1101010_00000_?????_0001011100_????? `define MTF_D 32'b1101010_00000_?????_1101011100_????? -`define MTFLH_D 32'b1101010_?????_?????_1101011101_????? +`define MTFLH_D 32'b1101010_?????_?????_1101111100_????? `define L_S 32'b1101000_?????_?????_010_???????????? `define L_D 32'b1101000_?????_?????_011_???????????? `define S_S 32'b1101001_?????_?????_010_???????????? diff --git a/instr-table.tex b/instr-table.tex index 4389fb4..ec043c5 100644 --- a/instr-table.tex +++ b/instr-table.tex @@ -1523,7 +1523,7 @@ \multicolumn{2}{|c|}{1101010} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{4}{c|}{1101011101} & +\multicolumn{4}{c|}{1101111100} & \multicolumn{1}{c|}{rdr} & MTFLH.D rdr,rs1,rs2 \\ \cline{2-10} diff --git a/update-opcodes b/update-opcodes index 1424ef5..75121e8 100755 --- a/update-opcodes +++ b/update-opcodes @@ -2,4 +2,5 @@ ./parse-opcodes -tex < opcodes > instr-table.tex ./parse-opcodes -verilog < opcodes > inst.v ./parse-opcodes -disasm < opcodes > ../xcc/src/include/opcode/mips-riscv-opc.h +./parse-opcodes -disasm < opcodes > ../pk/pk/riscv-opc.h ./parse-opcodes -switch < opcodes > ../sim/riscv/execute.h -- cgit v1.2.3