From a80067441555d749160d2bcc5362604c4ee91395 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@eecs.berkeley.edu>
Date: Mon, 9 Dec 2013 15:56:33 -0800
Subject: New RDCYCLE encoding

---
 inst.chisel     | 74 ++++++++++++++++++++++++++++-----------------------------
 instr-table.tex | 44 +++++++++++++++++-----------------
 opcodes-pseudo  | 10 ++++----
 parse-opcodes   | 71 +++++++++++++++++++++++++++---------------------------
 4 files changed, 99 insertions(+), 100 deletions(-)

diff --git a/inst.chisel b/inst.chisel
index 1b22a3e..0b68a65 100644
--- a/inst.chisel
+++ b/inst.chisel
@@ -181,60 +181,60 @@ object Instructions {
   def CUSTOM3_RD_RS1_RS2 = Bits("b?????????????????111?????1111011")
 }
 object CSRs {
-  val sup0 = 1280
-  val fflags = 1
-  val frm = 2
-  val fcsr = 3
-  val cycle = 4
-  val time = 5
-  val instret = 6
-  val sup1 = 1281
-  val evec = 1288
-  val cause = 1289
-  val status = 1290
-  val hartid = 1291
-  val impl = 1292
-  val epc = 1282
-  val send_ipi = 1294
-  val clear_ipi = 1295
-  val badvaddr = 1283
-  val ptbr = 1284
-  val stats = 1308
-  val reset = 1309
-  val tohost = 1310
-  val asid = 1285
-  val count = 1286
-  val compare = 1287
-  val fromhost = 1311
-  val fatc = 1293
+  val fflags = 0x1
+  val frm = 0x2
+  val fcsr = 0x3
+  val sup0 = 0x500
+  val sup1 = 0x501
+  val epc = 0x502
+  val badvaddr = 0x503
+  val ptbr = 0x504
+  val asid = 0x505
+  val count = 0x506
+  val compare = 0x507
+  val evec = 0x508
+  val cause = 0x509
+  val status = 0x50a
+  val hartid = 0x50b
+  val impl = 0x50c
+  val fatc = 0x50d
+  val send_ipi = 0x50e
+  val clear_ipi = 0x50f
+  val stats = 0x51c
+  val reset = 0x51d
+  val tohost = 0x51e
+  val fromhost = 0x51f
+  val cycle = 0xc00
+  val time = 0xc01
+  val instret = 0xc02
   val all = {
     val res = collection.mutable.ArrayBuffer[Int]()
-    res += sup0
     res += fflags
     res += frm
     res += fcsr
-    res += cycle
-    res += time
-    res += instret
+    res += sup0
     res += sup1
+    res += epc
+    res += badvaddr
+    res += ptbr
+    res += asid
+    res += count
+    res += compare
     res += evec
     res += cause
     res += status
     res += hartid
     res += impl
-    res += epc
+    res += fatc
     res += send_ipi
     res += clear_ipi
-    res += badvaddr
-    res += ptbr
     res += stats
     res += reset
     res += tohost
-    res += asid
-    res += count
-    res += compare
     res += fromhost
-    res += fatc
+    res += cycle
+    res += time
+    res += instret
     res.toArray
   }
 }
diff --git a/instr-table.tex b/instr-table.tex
index 4f2f5a8..8439617 100644
--- a/instr-table.tex
+++ b/instr-table.tex
@@ -472,8 +472,8 @@
   
 
 &
-\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{00100} &
+\multicolumn{4}{|c|}{1100000} &
+\multicolumn{2}{c|}{00000} &
 \multicolumn{1}{c|}{00000} &
 \multicolumn{1}{c|}{010} &
 \multicolumn{1}{c|}{rd} &
@@ -482,8 +482,8 @@
   
 
 &
-\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{00101} &
+\multicolumn{4}{|c|}{1100000} &
+\multicolumn{2}{c|}{00001} &
 \multicolumn{1}{c|}{00000} &
 \multicolumn{1}{c|}{010} &
 \multicolumn{1}{c|}{rd} &
@@ -492,8 +492,8 @@
   
 
 &
-\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{00110} &
+\multicolumn{4}{|c|}{1100000} &
+\multicolumn{2}{c|}{00010} &
 \multicolumn{1}{c|}{00000} &
 \multicolumn{1}{c|}{010} &
 \multicolumn{1}{c|}{rd} &
@@ -1437,40 +1437,40 @@
 &
 \multicolumn{4}{|c|}{0000000} &
 \multicolumn{2}{c|}{00011} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{001} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{010} &
 \multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1110011} & FSSR rd,rs1 \\
+\multicolumn{1}{c|}{1110011} & FRCSR rd \\
 \cline{2-11}
   
 
 &
 \multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{00011} &
+\multicolumn{2}{c|}{00010} &
 \multicolumn{1}{c|}{00000} &
 \multicolumn{1}{c|}{010} &
 \multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1110011} & FRSR rd \\
+\multicolumn{1}{c|}{1110011} & FRRM rd \\
 \cline{2-11}
   
 
 &
 \multicolumn{4}{|c|}{0000000} &
 \multicolumn{2}{c|}{00001} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{001} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{010} &
 \multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1110011} & FSFLAGS rd,rs1 \\
+\multicolumn{1}{c|}{1110011} & FRFLAGS rd \\
 \cline{2-11}
   
 
 &
 \multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{00001} &
-\multicolumn{1}{c|}{00000} &
-\multicolumn{1}{c|}{010} &
+\multicolumn{2}{c|}{00011} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{001} &
 \multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1110011} & FRFLAGS rd \\
+\multicolumn{1}{c|}{1110011} & FSCSR rd,rs1 \\
 \cline{2-11}
   
 
@@ -1486,11 +1486,11 @@
 
 &
 \multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{00010} &
-\multicolumn{1}{c|}{00000} &
-\multicolumn{1}{c|}{010} &
+\multicolumn{2}{c|}{00001} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{001} &
 \multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1110011} & FRRM rd \\
+\multicolumn{1}{c|}{1110011} & FSFLAGS rd,rs1 \\
 \cline{2-11}
   
 
diff --git a/opcodes-pseudo b/opcodes-pseudo
index 38a3887..a3abbb8 100644
--- a/opcodes-pseudo
+++ b/opcodes-pseudo
@@ -3,8 +3,8 @@
 @frflags   rd 19..15=0 31..20=0x001 14..12=2 6..2=0x1C 1..0=3
 @fsrm      rd rs1      31..20=0x002 14..12=1 6..2=0x1C 1..0=3
 @frrm      rd 19..15=0 31..20=0x002 14..12=2 6..2=0x1C 1..0=3
-@fssr      rd rs1      31..20=0x003 14..12=1 6..2=0x1C 1..0=3
-@frsr      rd 19..15=0 31..20=0x003 14..12=2 6..2=0x1C 1..0=3
-@rdcycle   rd 19..15=0 31..20=0x004 14..12=2 6..2=0x1C 1..0=3
-@rdtime    rd 19..15=0 31..20=0x005 14..12=2 6..2=0x1C 1..0=3
-@rdinstret rd 19..15=0 31..20=0x006 14..12=2 6..2=0x1C 1..0=3
+@fscsr     rd rs1      31..20=0x003 14..12=1 6..2=0x1C 1..0=3
+@frcsr     rd 19..15=0 31..20=0x003 14..12=2 6..2=0x1C 1..0=3
+@rdcycle   rd 19..15=0 31..20=0xC00 14..12=2 6..2=0x1C 1..0=3
+@rdtime    rd 19..15=0 31..20=0xC01 14..12=2 6..2=0x1C 1..0=3
+@rdinstret rd 19..15=0 31..20=0xC02 14..12=2 6..2=0x1C 1..0=3
diff --git a/parse-opcodes b/parse-opcodes
index 8b4b2ea..6c12a16 100755
--- a/parse-opcodes
+++ b/parse-opcodes
@@ -40,34 +40,34 @@ arglut['cimm6'] = (15,10)
 arglut['cimm10'] = (14,5)
 arglut['cimm5'] = (9,5)
 
-csrs = {
-  0x001 : 'fflags',
-  0x002 : 'frm',
-  0x003 : 'fcsr',
-  0x004 : 'cycle',
-  0x005 : 'time',
-  0x006 : 'instret',
-  0x500 : 'sup0',
-  0x501 : 'sup1',
-  0x502 : 'epc',
-  0x503 : 'badvaddr',
-  0x504 : 'ptbr',
-  0x505 : 'asid',
-  0x506 : 'count',
-  0x507 : 'compare',
-  0x508 : 'evec',
-  0x509 : 'cause',
-  0x50A : 'status',
-  0x50B : 'hartid',
-  0x50C : 'impl',
-  0x50D : 'fatc',
-  0x50E : 'send_ipi',
-  0x50F : 'clear_ipi',
-  0x51C : 'stats', # XXX
-  0x51D : 'reset',
-  0x51E : 'tohost',
-  0x51F : 'fromhost',
-}
+csrs = [
+  (0x001, 'fflags'),
+  (0x002, 'frm'),
+  (0x003, 'fcsr'),
+  (0x500, 'sup0'),
+  (0x501, 'sup1'),
+  (0x502, 'epc'),
+  (0x503, 'badvaddr'),
+  (0x504, 'ptbr'),
+  (0x505, 'asid'),
+  (0x506, 'count'),
+  (0x507, 'compare'),
+  (0x508, 'evec'),
+  (0x509, 'cause'),
+  (0x50A, 'status'),
+  (0x50B, 'hartid'),
+  (0x50C, 'impl'),
+  (0x50D, 'fatc'),
+  (0x50E, 'send_ipi'),
+  (0x50F, 'clear_ipi'),
+  (0x51C, 'stats'), # XXX
+  (0x51D, 'reset'),
+  (0x51E, 'tohost'),
+  (0x51F, 'fromhost'),
+  (0xC00, 'cycle'),
+  (0xC01, 'time'),
+  (0xC02, 'instret'),
+]
 
 opcode_base = 0
 opcode_size = 7
@@ -86,7 +86,7 @@ def make_c(match,mask):
     name2 = name.upper().replace('.','_')
     print '#define MATCH_%s %s' % (name2, hex(match[name]))
     print '#define MASK_%s  %s' % (name2, hex(mask[name]))
-  for num, name in csrs.items():
+  for num, name in csrs:
     print '#define CSR_%s %s' % (name.upper(), hex(num))
   print '#endif'
 
@@ -97,7 +97,7 @@ def make_c(match,mask):
   print '#endif'
 
   print '#ifdef DECLARE_CSR'
-  for num, name in csrs.items():
+  for num, name in csrs:
     print 'DECLARE_CSR(%s, CSR_%s)' % (name, name.upper())
   print '#endif'
 
@@ -564,9 +564,8 @@ def make_latex_table():
   print_insts('fcvt.s.w', 'fcvt.s.wu', 'fmv.s.x')
   print_insts('fcvt.w.s', 'fcvt.wu.s', 'fmv.x.s')
   print_insts('feq.s', 'flt.s', 'fle.s')
-  print_insts('fssr', 'frsr')
-  print_insts('fsflags', 'frflags')
-  print_insts('fsrm', 'frrm')
+  print_insts('frcsr', 'frrm', 'frflags')
+  print_insts('fscsr', 'fsrm', 'fsflags')
   print_footer(0)
 
   print_header('r','r4','i','s')
@@ -603,11 +602,11 @@ def make_chisel():
     print_chisel_insn(name)
   print '}'
   print 'object CSRs {'
-  for num, name in csrs.items():
-    print '  val %s = %d' % (name, num)
+  for num, name in csrs:
+    print '  val %s = %s' % (name, hex(num))
   print '  val all = {'
   print '    val res = collection.mutable.ArrayBuffer[Int]()'
-  for num, name in csrs.items():
+  for num, name in csrs:
     print '    res += %s' % (name)
   print '    res.toArray'
   print '  }'
-- 
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