From 91615aeaf5e3f97a9a34375e911cd001c599a976 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 25 Oct 2010 19:41:39 -0700 Subject: [sim,xcc,pk,opcodes] static rounding modes for FP insns Now, you can either use the RM in the FSR or specify it in the insn. (Except for FP->int; no dynamic for that.) --- .opcodes.swp | Bin 0 -> 16384 bytes inst.v | 61 +++++++++++++++++++++++---------- instr-table.tex | 104 +++++++++----------------------------------------------- opcodes | 72 ++++++++++++++++++++++++++++----------- parse-opcodes | 42 ++++++++++++++++++++++- 5 files changed, 152 insertions(+), 127 deletions(-) create mode 100644 .opcodes.swp diff --git a/.opcodes.swp b/.opcodes.swp new file mode 100644 index 0000000..e728d76 Binary files /dev/null and b/.opcodes.swp differ diff --git a/inst.v b/inst.v index dfd8e44..ed0bd15 100644 --- a/inst.v +++ b/inst.v @@ -109,14 +109,24 @@ `define SGNINJ_D 32'b1101010_?????_?????_1100000101_????? `define SGNINJN_D 32'b1101010_?????_?????_1100000110_????? `define SGNMUL_D 32'b1101010_?????_?????_1100000111_????? -`define TRUNC_L_S 32'b1101010_00000_?????_0000001000_????? -`define TRUNCU_L_S 32'b1101010_00000_?????_0000001001_????? -`define TRUNC_W_S 32'b1101010_00000_?????_0000001010_????? -`define TRUNCU_W_S 32'b1101010_00000_?????_0000001011_????? -`define TRUNC_L_D 32'b1101010_00000_?????_1100001000_????? -`define TRUNCU_L_D 32'b1101010_00000_?????_1100001001_????? -`define TRUNC_W_D 32'b1101010_00000_?????_1100001010_????? -`define TRUNCU_W_D 32'b1101010_00000_?????_1100001011_????? +`define ADD_S_RM 32'b1101010_?????_?????_00_??_100000_????? +`define SUB_S_RM 32'b1101010_?????_?????_00_??_100001_????? +`define MUL_S_RM 32'b1101010_?????_?????_00_??_100010_????? +`define DIV_S_RM 32'b1101010_?????_?????_00_??_100011_????? +`define SQRT_S_RM 32'b1101010_00000_?????_00_??_100100_????? +`define ADD_D_RM 32'b1101010_?????_?????_11_??_100000_????? +`define SUB_D_RM 32'b1101010_?????_?????_11_??_100001_????? +`define MUL_D_RM 32'b1101010_?????_?????_11_??_100010_????? +`define DIV_D_RM 32'b1101010_?????_?????_11_??_100011_????? +`define SQRT_D_RM 32'b1101010_00000_?????_11_??_100100_????? +`define CVT_L_S_RM 32'b1101010_00000_?????_00_??_101000_????? +`define CVTU_L_S_RM 32'b1101010_00000_?????_00_??_101001_????? +`define CVT_W_S_RM 32'b1101010_00000_?????_00_??_101010_????? +`define CVTU_W_S_RM 32'b1101010_00000_?????_00_??_101011_????? +`define CVT_L_D_RM 32'b1101010_00000_?????_11_??_101000_????? +`define CVTU_L_D_RM 32'b1101010_00000_?????_11_??_101001_????? +`define CVT_W_D_RM 32'b1101010_00000_?????_11_??_101010_????? +`define CVTU_W_D_RM 32'b1101010_00000_?????_11_??_101011_????? `define CVT_S_L 32'b1101010_00000_?????_0000001100_????? `define CVTU_S_L 32'b1101010_00000_?????_0000001101_????? `define CVT_S_W 32'b1101010_00000_?????_0000001110_????? @@ -125,8 +135,15 @@ `define CVTU_D_L 32'b1101010_00000_?????_1100001101_????? `define CVT_D_W 32'b1101010_00000_?????_1100001110_????? `define CVTU_D_W 32'b1101010_00000_?????_1100001111_????? -`define CVT_S_D 32'b1101010_00000_?????_0000110011_????? -`define CVT_D_S 32'b1101010_00000_?????_1100110000_????? +`define CVT_S_L_RM 32'b1101010_00000_?????_00_??_101100_????? +`define CVTU_S_L_RM 32'b1101010_00000_?????_00_??_101101_????? +`define CVT_S_W_RM 32'b1101010_00000_?????_00_??_101110_????? +`define CVTU_S_W_RM 32'b1101010_00000_?????_00_??_101111_????? +`define CVT_D_L_RM 32'b1101010_00000_?????_11_??_101100_????? +`define CVTU_D_L_RM 32'b1101010_00000_?????_11_??_101101_????? +`define CVT_S_D 32'b1101010_00000_?????_0000010011_????? +`define CVT_D_S 32'b1101010_00000_?????_1100010000_????? +`define CVT_S_D_RM 32'b1101010_00000_?????_00_??_110011_????? `define C_EQ_S 32'b1101010_?????_?????_0000010101_????? `define C_LT_S 32'b1101010_?????_?????_0000010110_????? `define C_LE_S 32'b1101010_?????_?????_0000010111_????? @@ -144,11 +161,19 @@ `define L_D 32'b1101000_?????_?????_011_???????????? `define S_S 32'b1101001_?????_?????_010_???????????? `define S_D 32'b1101001_?????_?????_011_???????????? -`define MADD_S 32'b1101011_?????_?????_00000_?????_????? -`define MSUB_S 32'b1101011_?????_?????_00001_?????_????? -`define NMSUB_S 32'b1101011_?????_?????_00010_?????_????? -`define NMADD_S 32'b1101011_?????_?????_00011_?????_????? -`define MADD_D 32'b1101011_?????_?????_11000_?????_????? -`define MSUB_D 32'b1101011_?????_?????_11001_?????_????? -`define NMSUB_D 32'b1101011_?????_?????_11010_?????_????? -`define NMADD_D 32'b1101011_?????_?????_11011_?????_????? +`define MADD_S 32'b1101100_?????_?????_00000_?????_????? +`define MSUB_S 32'b1101101_?????_?????_00000_?????_????? +`define NMSUB_S 32'b1101110_?????_?????_00000_?????_????? +`define NMADD_S 32'b1101111_?????_?????_00000_?????_????? +`define MADD_D 32'b1101100_?????_?????_11000_?????_????? +`define MSUB_D 32'b1101101_?????_?????_11000_?????_????? +`define NMSUB_D 32'b1101110_?????_?????_11000_?????_????? +`define NMADD_D 32'b1101111_?????_?????_11000_?????_????? +`define MADD_S_RM 32'b1101100_?????_?????_00_??_1_?????_????? +`define MSUB_S_RM 32'b1101101_?????_?????_00_??_1_?????_????? +`define NMSUB_S_RM 32'b1101110_?????_?????_00_??_1_?????_????? +`define NMADD_S_RM 32'b1101111_?????_?????_00_??_1_?????_????? +`define MADD_D_RM 32'b1101100_?????_?????_11_??_1_?????_????? +`define MSUB_D_RM 32'b1101101_?????_?????_11_??_1_?????_????? +`define NMSUB_D_RM 32'b1101110_?????_?????_11_??_1_?????_????? +`define NMADD_D_RM 32'b1101111_?????_?????_11_??_1_?????_????? diff --git a/instr-table.tex b/instr-table.tex index bbb3fae..c9dfab6 100644 --- a/instr-table.tex +++ b/instr-table.tex @@ -1146,7 +1146,7 @@ & -\multicolumn{2}{|c|}{1101011} & +\multicolumn{2}{|c|}{1101100} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{2}{c|}{00000} & @@ -1156,37 +1156,37 @@ & -\multicolumn{2}{|c|}{1101011} & +\multicolumn{2}{|c|}{1101101} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{00001} & +\multicolumn{2}{c|}{00000} & \multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rdr} & MSUB.S rdr,rs1,rs2,rs3 \\ \cline{2-10} & -\multicolumn{2}{|c|}{1101011} & +\multicolumn{2}{|c|}{1101110} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{00010} & +\multicolumn{2}{c|}{00000} & \multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rdr} & NMSUB.S rdr,rs1,rs2,rs3 \\ \cline{2-10} & -\multicolumn{2}{|c|}{1101011} & +\multicolumn{2}{|c|}{1101111} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{00011} & +\multicolumn{2}{c|}{00000} & \multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rdr} & NMADD.S rdr,rs1,rs2,rs3 \\ \cline{2-10} & -\multicolumn{2}{|c|}{1101011} & +\multicolumn{2}{|c|}{1101100} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & \multicolumn{2}{c|}{11000} & @@ -1196,30 +1196,30 @@ & -\multicolumn{2}{|c|}{1101011} & +\multicolumn{2}{|c|}{1101101} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{11001} & +\multicolumn{2}{c|}{11000} & \multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rdr} & MSUB.D rdr,rs1,rs2,rs3 \\ \cline{2-10} & -\multicolumn{2}{|c|}{1101011} & +\multicolumn{2}{|c|}{1101110} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{11010} & +\multicolumn{2}{c|}{11000} & \multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rdr} & NMSUB.D rdr,rs1,rs2,rs3 \\ \cline{2-10} & -\multicolumn{2}{|c|}{1101011} & +\multicolumn{2}{|c|}{1101111} & \multicolumn{1}{c|}{rs2} & \multicolumn{1}{c|}{rs1} & -\multicolumn{2}{c|}{11011} & +\multicolumn{2}{c|}{11000} & \multicolumn{2}{c|}{rs3} & \multicolumn{1}{c|}{rdr} & NMADD.D rdr,rs1,rs2,rs3 \\ \cline{2-10} @@ -1351,7 +1351,7 @@ \multicolumn{2}{|c|}{1101010} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{4}{c|}{0000110011} & +\multicolumn{4}{c|}{0000010011} & \multicolumn{1}{c|}{rdr} & CVT.S.D rdr,rs1 \\ \cline{2-10} @@ -1360,7 +1360,7 @@ \multicolumn{2}{|c|}{1101010} & \multicolumn{1}{c|}{00000} & \multicolumn{1}{c|}{rs1} & -\multicolumn{4}{c|}{1100110000} & +\multicolumn{4}{c|}{1100010000} & \multicolumn{1}{c|}{rdr} & CVT.D.S rdr,rs1 \\ \cline{2-10} @@ -1553,78 +1553,6 @@ \cline{2-10} -& -\multicolumn{2}{|c|}{1101010} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{4}{c|}{0000001000} & -\multicolumn{1}{c|}{rdr} & TRUNC.L.S rdr,rs1 \\ -\cline{2-10} - - -& -\multicolumn{2}{|c|}{1101010} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{4}{c|}{0000001001} & -\multicolumn{1}{c|}{rdr} & TRUNCU.L.S rdr,rs1 \\ -\cline{2-10} - - -& -\multicolumn{2}{|c|}{1101010} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{4}{c|}{0000001010} & -\multicolumn{1}{c|}{rdr} & TRUNC.W.S rdr,rs1 \\ -\cline{2-10} - - -& -\multicolumn{2}{|c|}{1101010} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{4}{c|}{0000001011} & -\multicolumn{1}{c|}{rdr} & TRUNCU.W.S rdr,rs1 \\ -\cline{2-10} - - -& -\multicolumn{2}{|c|}{1101010} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{4}{c|}{1100001000} & -\multicolumn{1}{c|}{rdr} & TRUNC.L.D rdr,rs1 \\ -\cline{2-10} - - -& -\multicolumn{2}{|c|}{1101010} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{4}{c|}{1100001001} & -\multicolumn{1}{c|}{rdr} & TRUNCU.L.D rdr,rs1 \\ -\cline{2-10} - - -& -\multicolumn{2}{|c|}{1101010} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{4}{c|}{1100001010} & -\multicolumn{1}{c|}{rdr} & TRUNC.W.D rdr,rs1 \\ -\cline{2-10} - - -& -\multicolumn{2}{|c|}{1101010} & -\multicolumn{1}{c|}{00000} & -\multicolumn{1}{c|}{rs1} & -\multicolumn{4}{c|}{1100001011} & -\multicolumn{1}{c|}{rdr} & TRUNCU.W.D rdr,rs1 \\ -\cline{2-10} - - & \multicolumn{2}{|c|}{1101010} & \multicolumn{1}{c|}{rs2} & diff --git a/opcodes b/opcodes index ecb066e..43d41e1 100644 --- a/opcodes +++ b/opcodes @@ -139,15 +139,27 @@ sgninj.d 31..25=0x6A 14..13=3 12..10=0 9..5=0x5 rdr rs1 rs2 sgninjn.d 31..25=0x6A 14..13=3 12..10=0 9..5=0x6 rdr rs1 rs2 sgnmul.d 31..25=0x6A 14..13=3 12..10=0 9..5=0x7 rdr rs1 rs2 -trunc.l.s 31..25=0x6A 14..13=0 12..10=0 9..5=0x8 24..20=0 rdr rs1 -truncu.l.s 31..25=0x6A 14..13=0 12..10=0 9..5=0x9 24..20=0 rdr rs1 -trunc.w.s 31..25=0x6A 14..13=0 12..10=0 9..5=0xA 24..20=0 rdr rs1 -truncu.w.s 31..25=0x6A 14..13=0 12..10=0 9..5=0xB 24..20=0 rdr rs1 - -trunc.l.d 31..25=0x6A 14..13=3 12..10=0 9..5=0x8 24..20=0 rdr rs1 -truncu.l.d 31..25=0x6A 14..13=3 12..10=0 9..5=0x9 24..20=0 rdr rs1 -trunc.w.d 31..25=0x6A 14..13=3 12..10=0 9..5=0xA 24..20=0 rdr rs1 -truncu.w.d 31..25=0x6A 14..13=3 12..10=0 9..5=0xB 24..20=0 rdr rs1 +add.s.rm 31..25=0x6A 14..13=0 10=1 9..5=0 rdr rs1 rs2 rm +sub.s.rm 31..25=0x6A 14..13=0 10=1 9..5=1 rdr rs1 rs2 rm +mul.s.rm 31..25=0x6A 14..13=0 10=1 9..5=2 rdr rs1 rs2 rm +div.s.rm 31..25=0x6A 14..13=0 10=1 9..5=3 rdr rs1 rs2 rm +sqrt.s.rm 31..25=0x6A 14..13=0 10=1 9..5=4 24..20=0 rdr rs1 rm + +add.d.rm 31..25=0x6A 14..13=3 10=1 9..5=0x0 rdr rs1 rs2 rm +sub.d.rm 31..25=0x6A 14..13=3 10=1 9..5=0x1 rdr rs1 rs2 rm +mul.d.rm 31..25=0x6A 14..13=3 10=1 9..5=0x2 rdr rs1 rs2 rm +div.d.rm 31..25=0x6A 14..13=3 10=1 9..5=0x3 rdr rs1 rs2 rm +sqrt.d.rm 31..25=0x6A 14..13=3 10=1 9..5=0x4 24..20=0 rdr rs1 rm + +cvt.l.s.rm 31..25=0x6A 14..13=0 10=1 9..5=0x8 24..20=0 rdr rs1 rm +cvtu.l.s.rm 31..25=0x6A 14..13=0 10=1 9..5=0x9 24..20=0 rdr rs1 rm +cvt.w.s.rm 31..25=0x6A 14..13=0 10=1 9..5=0xA 24..20=0 rdr rs1 rm +cvtu.w.s.rm 31..25=0x6A 14..13=0 10=1 9..5=0xB 24..20=0 rdr rs1 rm + +cvt.l.d.rm 31..25=0x6A 14..13=3 10=1 9..5=0x8 24..20=0 rdr rs1 rm +cvtu.l.d.rm 31..25=0x6A 14..13=3 10=1 9..5=0x9 24..20=0 rdr rs1 rm +cvt.w.d.rm 31..25=0x6A 14..13=3 10=1 9..5=0xA 24..20=0 rdr rs1 rm +cvtu.w.d.rm 31..25=0x6A 14..13=3 10=1 9..5=0xB 24..20=0 rdr rs1 rm cvt.s.l 31..25=0x6A 14..13=0 12..10=0 9..5=0xC 24..20=0 rdr rs1 cvtu.s.l 31..25=0x6A 14..13=0 12..10=0 9..5=0xD 24..20=0 rdr rs1 @@ -159,8 +171,18 @@ cvtu.d.l 31..25=0x6A 14..13=3 12..10=0 9..5=0xD 24..20=0 rdr rs1 cvt.d.w 31..25=0x6A 14..13=3 12..10=0 9..5=0xE 24..20=0 rdr rs1 cvtu.d.w 31..25=0x6A 14..13=3 12..10=0 9..5=0xF 24..20=0 rdr rs1 -cvt.s.d 31..25=0x6A 14..13=0 12..10=1 9..5=0x13 24..20=0 rdr rs1 -cvt.d.s 31..25=0x6A 14..13=3 12..10=1 9..5=0x10 24..20=0 rdr rs1 +cvt.s.l.rm 31..25=0x6A 14..13=0 10=1 9..5=0xC 24..20=0 rdr rs1 rm +cvtu.s.l.rm 31..25=0x6A 14..13=0 10=1 9..5=0xD 24..20=0 rdr rs1 rm +cvt.s.w.rm 31..25=0x6A 14..13=0 10=1 9..5=0xE 24..20=0 rdr rs1 rm +cvtu.s.w.rm 31..25=0x6A 14..13=0 10=1 9..5=0xF 24..20=0 rdr rs1 rm + +cvt.d.l.rm 31..25=0x6A 14..13=3 10=1 9..5=0xC 24..20=0 rdr rs1 rm +cvtu.d.l.rm 31..25=0x6A 14..13=3 10=1 9..5=0xD 24..20=0 rdr rs1 rm + +cvt.s.d 31..25=0x6A 14..13=0 12..10=0 9..5=0x13 24..20=0 rdr rs1 +cvt.d.s 31..25=0x6A 14..13=3 12..10=0 9..5=0x10 24..20=0 rdr rs1 + +cvt.s.d.rm 31..25=0x6A 14..13=0 10=1 9..5=0x13 24..20=0 rdr rs1 rm c.eq.s 31..25=0x6A 14..13=0 12..10=0 9..5=0x15 rdr rs1 rs2 c.lt.s 31..25=0x6A 14..13=0 12..10=0 9..5=0x16 rdr rs1 rs2 @@ -184,13 +206,23 @@ l.d 31..25=0x68 14..12=3 rdi rs1 imm12 s.s 31..25=0x69 14..12=2 rs2 rs1 imm12 s.d 31..25=0x69 14..12=3 rs2 rs1 imm12 -madd.s 31..25=0x6B 14..13=0 12..10=0 rdr rs1 rs2 rs3 -msub.s 31..25=0x6B 14..13=0 12..10=1 rdr rs1 rs2 rs3 -nmsub.s 31..25=0x6B 14..13=0 12..10=2 rdr rs1 rs2 rs3 -nmadd.s 31..25=0x6B 14..13=0 12..10=3 rdr rs1 rs2 rs3 - -madd.d 31..25=0x6B 14..13=3 12..10=0 rdr rs1 rs2 rs3 -msub.d 31..25=0x6B 14..13=3 12..10=1 rdr rs1 rs2 rs3 -nmsub.d 31..25=0x6B 14..13=3 12..10=2 rdr rs1 rs2 rs3 -nmadd.d 31..25=0x6B 14..13=3 12..10=3 rdr rs1 rs2 rs3 +madd.s 31..25=0x6C 14..13=0 12..10=0 rdr rs1 rs2 rs3 +msub.s 31..25=0x6D 14..13=0 12..10=0 rdr rs1 rs2 rs3 +nmsub.s 31..25=0x6E 14..13=0 12..10=0 rdr rs1 rs2 rs3 +nmadd.s 31..25=0x6F 14..13=0 12..10=0 rdr rs1 rs2 rs3 + +madd.d 31..25=0x6C 14..13=3 12..10=0 rdr rs1 rs2 rs3 +msub.d 31..25=0x6D 14..13=3 12..10=0 rdr rs1 rs2 rs3 +nmsub.d 31..25=0x6E 14..13=3 12..10=0 rdr rs1 rs2 rs3 +nmadd.d 31..25=0x6F 14..13=3 12..10=0 rdr rs1 rs2 rs3 + +madd.s.rm 31..25=0x6C 14..13=0 10=1 rdr rs1 rs2 rs3 rm +msub.s.rm 31..25=0x6D 14..13=0 10=1 rdr rs1 rs2 rs3 rm +nmsub.s.rm 31..25=0x6E 14..13=0 10=1 rdr rs1 rs2 rs3 rm +nmadd.s.rm 31..25=0x6F 14..13=0 10=1 rdr rs1 rs2 rs3 rm + +madd.d.rm 31..25=0x6C 14..13=3 10=1 rdr rs1 rs2 rs3 rm +msub.d.rm 31..25=0x6D 14..13=3 10=1 rdr rs1 rs2 rs3 rm +nmsub.d.rm 31..25=0x6E 14..13=3 10=1 rdr rs1 rs2 rs3 rm +nmadd.d.rm 31..25=0x6F 14..13=3 10=1 rdr rs1 rs2 rs3 rm diff --git a/parse-opcodes b/parse-opcodes index 2f14253..b3b93ab 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -21,6 +21,7 @@ arglut['imm20'] = (19,0) arglut['imm12'] = (11,0) arglut['shamt'] = (5,0) arglut['shamtw'] = (4,0) +arglut['rm'] = (12,11) typelut = {} # 0=unimp,1=j,2=lui,3=imm,4=r,5=r4,6=ish,7=ishw typelut[0x00] = 0 @@ -40,7 +41,10 @@ typelut[0x7e] = 4 typelut[0x68] = 3 typelut[0x69] = 3 typelut[0x6a] = 4 -typelut[0x6b] = 5 +typelut[0x6c] = 5 +typelut[0x6d] = 5 +typelut[0x6e] = 5 +typelut[0x6f] = 5 def binary(n, digits=0): rep = bin(n)[2:] @@ -576,6 +580,33 @@ def print_verilog_r4_type(name,match,arguments): str_verilog_arg('rdr','',match,arguments) \ ) +def print_verilog_r4_rm_type(name,match,arguments): + print "`define %-10s 32'b%s_%s_%s_%s_%s_%s_%s_%s" % \ + ( \ + name.replace('.','_').upper(), \ + binary(yank(match,25,7),7), \ + str_verilog_arg('rs2','',match,arguments), \ + str_verilog_arg('rs1','',match,arguments), \ + binary(yank(match,13,2),2), \ + str_verilog_arg('rm','',match,arguments), \ + binary(yank(match,10,1),1), \ + str_verilog_arg('rs3','',match,arguments), \ + str_verilog_arg('rdr','',match,arguments) \ + ) + +def print_verilog_r_rm_type(name,match,arguments): + print "`define %-10s 32'b%s_%s_%s_%s_%s_%s_%s" % \ + ( \ + name.replace('.','_').upper(), \ + binary(yank(match,25,7),7), \ + str_verilog_arg('rs2','',match,arguments), \ + str_verilog_arg('rs1','',match,arguments), \ + binary(yank(match,13,2),2), \ + str_verilog_arg('rm','',match,arguments), \ + binary(yank(match,5,6),6), \ + str_verilog_arg('rdr','',match,arguments) \ + ) + def print_verilog_r_type(name,match,arguments): print "`define %-10s 32'b%s_%s_%s_%s_%s" % \ ( \ @@ -605,6 +636,10 @@ def make_verilog(): print_verilog_ish_type(name,match[name],arguments[name]) elif types[name] == 7: print_verilog_ishw_type(name,match[name],arguments[name]) + elif types[name] == 8: + print_verilog_r4_rm_type(name,match[name],arguments[name]) + elif types[name] == 9: + print_verilog_r_rm_type(name,match[name],arguments[name]) for line in sys.stdin: line = line.partition('#') @@ -664,6 +699,11 @@ for line in sys.stdin: types[name] = 7 elif 'shamt' in arguments[name]: types[name] = 6 + elif types[name] == 5 and 'rm' in arguments[name]: + types[name] = 8 + elif types[name] == 4 and 'rm' in arguments[name]: + types[name] = 9 + namelist.append(name) if sys.argv[1] == '-tex': -- cgit v1.2.3