From 6587f83bc6708e7971e024fb25f747927975b993 Mon Sep 17 00:00:00 2001
From: Yunsup Lee <yunsup@cs.berkeley.edu>
Date: Fri, 26 Jul 2013 19:00:15 -0700
Subject: tweaks

---
 instr-table.tex | 152 ++++++++++++++++++++++++++++++++------------------------
 parse-opcodes   |  24 +++++----
 2 files changed, 100 insertions(+), 76 deletions(-)

diff --git a/instr-table.tex b/instr-table.tex
index 6c4c84b..f4393b1 100644
--- a/instr-table.tex
+++ b/instr-table.tex
@@ -10,11 +10,11 @@
 \instbitrange{26}{22} &
 \instbitrange{21}{17} &
 \instbit{16} &
-\instbit{15} &
-\instbitrange{14}{12} &
+ &
+\instbitrange{}{12} &
 \instbitrange{11}{10} &
 \instbit{9} &
-\instbitrange{8}{7} &
+\instbitrange{}{7} &
 \instbitrange{6}{0} \\
 \cline{2-11}
 &
@@ -507,11 +507,11 @@
 \instbitrange{26}{22} &
 \instbitrange{21}{17} &
 \instbit{16} &
-\instbit{15} &
-\instbitrange{14}{12} &
+ &
+\instbitrange{}{12} &
 \instbitrange{11}{10} &
 \instbit{9} &
-\instbitrange{8}{7} &
+\instbitrange{}{7} &
 \instbitrange{6}{0} \\
 \cline{2-11}
 &
@@ -559,7 +559,7 @@
 &
 \multicolumn{10}{c}{} & \\
 &
-\multicolumn{10}{c}{\bf RV64I Instruction Subset} & \\
+\multicolumn{10}{c}{\bf RV64I Instruction Subset (in addition to RV32I)} & \\
 \cline{2-11}
   
 
@@ -770,7 +770,7 @@
 &
 \multicolumn{10}{c}{} & \\
 &
-\multicolumn{10}{c}{\bf RV64M Instruction Subset} & \\
+\multicolumn{10}{c}{\bf RV64M Instruction Subset (in addition to RV32M)} & \\
 \cline{2-11}
   
 
@@ -950,11 +950,11 @@
 \instbitrange{26}{22} &
 \instbitrange{21}{17} &
 \instbit{16} &
-\instbit{15} &
-\instbitrange{14}{12} &
+ &
+\instbitrange{}{12} &
 \instbitrange{11}{10} &
 \instbit{9} &
-\instbitrange{8}{7} &
+\instbitrange{}{7} &
 \instbitrange{6}{0} \\
 \cline{2-11}
 &
@@ -1002,7 +1002,7 @@
 &
 \multicolumn{10}{c}{} & \\
 &
-\multicolumn{10}{c}{\bf RV64A Instruction Subset} & \\
+\multicolumn{10}{c}{\bf RV64A Instruction Subset (in addition to RV32A)} & \\
 \cline{2-11}
   
 
@@ -1191,8 +1191,9 @@
 \multicolumn{1}{|c|}{rd} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{rs2} &
-\multicolumn{4}{c|}{1100000} &
+\multicolumn{3}{c|}{11000} &
 \multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{00} &
 \multicolumn{1}{c|}{1010011} & FMIN.S rd,rs1,rs2 \\
 \cline{2-11}
   
@@ -1201,8 +1202,9 @@
 \multicolumn{1}{|c|}{rd} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{rs2} &
-\multicolumn{4}{c|}{1100100} &
+\multicolumn{3}{c|}{11001} &
 \multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{00} &
 \multicolumn{1}{c|}{1010011} & FMAX.S rd,rs1,rs2 \\
 \cline{2-11}
   
@@ -1255,8 +1257,9 @@
 \multicolumn{1}{|c|}{rd} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{rs2} &
-\multicolumn{4}{c|}{0010100} &
+\multicolumn{3}{c|}{00101} &
 \multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{00} &
 \multicolumn{1}{c|}{1010011} & FSGNJ.S rd,rs1,rs2 \\
 \cline{2-11}
   
@@ -1265,8 +1268,9 @@
 \multicolumn{1}{|c|}{rd} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{rs2} &
-\multicolumn{4}{c|}{0011000} &
+\multicolumn{3}{c|}{00110} &
 \multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{00} &
 \multicolumn{1}{c|}{1010011} & FSGNJN.S rd,rs1,rs2 \\
 \cline{2-11}
   
@@ -1275,8 +1279,9 @@
 \multicolumn{1}{|c|}{rd} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{rs2} &
-\multicolumn{4}{c|}{0011100} &
+\multicolumn{3}{c|}{00111} &
 \multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{00} &
 \multicolumn{1}{c|}{1010011} & FSGNJX.S rd,rs1,rs2 \\
 \cline{2-11}
   
@@ -1307,22 +1312,13 @@
 \multicolumn{1}{|c|}{rd} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{00000} &
-\multicolumn{4}{c|}{1111000} &
+\multicolumn{3}{c|}{11110} &
 \multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{00} &
 \multicolumn{1}{c|}{1010011} & FMV.S.X rd,rs1 \\
 \cline{2-11}
   
 
-&
-\multicolumn{1}{|c|}{rd} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{00000} &
-\multicolumn{4}{c|}{1111100} &
-\multicolumn{2}{c|}{000} &
-\multicolumn{1}{c|}{1010011} & MTFSR rd,rs1 \\
-\cline{2-11}
-  
-
 &
 \multicolumn{1}{|c|}{rd} &
 \multicolumn{1}{c|}{rs1} &
@@ -1349,19 +1345,21 @@
 \multicolumn{1}{|c|}{rd} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{00000} &
-\multicolumn{4}{c|}{1110000} &
+\multicolumn{3}{c|}{11100} &
 \multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{00} &
 \multicolumn{1}{c|}{1010011} & FMV.X.S rd,rs1 \\
 \cline{2-11}
   
 
 &
 \multicolumn{1}{|c|}{rd} &
-\multicolumn{1}{c|}{00000} &
-\multicolumn{1}{c|}{00000} &
-\multicolumn{4}{c|}{1110100} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{3}{c|}{10101} &
 \multicolumn{2}{c|}{000} &
-\multicolumn{1}{c|}{1010011} & MFFSR rd \\
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & FEQ.S rd,rs1,rs2 \\
 \cline{2-11}
   
 
@@ -1369,9 +1367,10 @@
 \multicolumn{1}{|c|}{rd} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{rs2} &
-\multicolumn{4}{c|}{1010100} &
+\multicolumn{3}{c|}{10110} &
 \multicolumn{2}{c|}{000} &
-\multicolumn{1}{c|}{1010011} & FEQ.S rd,rs1,rs2 \\
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & FLT.S rd,rs1,rs2 \\
 \cline{2-11}
   
 
@@ -1379,19 +1378,32 @@
 \multicolumn{1}{|c|}{rd} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{rs2} &
-\multicolumn{4}{c|}{1011000} &
+\multicolumn{3}{c|}{10111} &
 \multicolumn{2}{c|}{000} &
-\multicolumn{1}{c|}{1010011} & FLT.S rd,rs1,rs2 \\
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & FLE.S rd,rs1,rs2 \\
 \cline{2-11}
   
 
 &
 \multicolumn{1}{|c|}{rd} &
 \multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rs2} &
-\multicolumn{4}{c|}{1011100} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{3}{c|}{11111} &
 \multicolumn{2}{c|}{000} &
-\multicolumn{1}{c|}{1010011} & FLE.S rd,rs1,rs2 \\
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & MTFSR rd,rs1 \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{3}{c|}{11101} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{00} &
+\multicolumn{1}{c|}{1010011} & MFFSR rd \\
 \cline{2-11}
   
 
@@ -1414,11 +1426,11 @@
 \instbitrange{26}{22} &
 \instbitrange{21}{17} &
 \instbit{16} &
-\instbit{15} &
-\instbitrange{14}{12} &
+ &
+\instbitrange{}{12} &
 \instbitrange{11}{10} &
 \instbit{9} &
-\instbitrange{8}{7} &
+\instbitrange{}{7} &
 \instbitrange{6}{0} \\
 \cline{2-11}
 &
@@ -1466,7 +1478,7 @@
 &
 \multicolumn{10}{c}{} & \\
 &
-\multicolumn{10}{c}{\bf RV64F Instruction Subset} & \\
+\multicolumn{10}{c}{\bf RV64F Instruction Subset (in addition to RV32F)} & \\
 \cline{2-11}
   
 
@@ -1599,8 +1611,9 @@
 \multicolumn{1}{|c|}{rd} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{rs2} &
-\multicolumn{4}{c|}{1100000} &
-\multicolumn{2}{c|}{001} &
+\multicolumn{3}{c|}{11000} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{01} &
 \multicolumn{1}{c|}{1010011} & FMIN.D rd,rs1,rs2 \\
 \cline{2-11}
   
@@ -1609,8 +1622,9 @@
 \multicolumn{1}{|c|}{rd} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{rs2} &
-\multicolumn{4}{c|}{1100100} &
-\multicolumn{2}{c|}{001} &
+\multicolumn{3}{c|}{11001} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{01} &
 \multicolumn{1}{c|}{1010011} & FMAX.D rd,rs1,rs2 \\
 \cline{2-11}
   
@@ -1663,8 +1677,9 @@
 \multicolumn{1}{|c|}{rd} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{rs2} &
-\multicolumn{4}{c|}{0010100} &
-\multicolumn{2}{c|}{001} &
+\multicolumn{3}{c|}{00101} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{01} &
 \multicolumn{1}{c|}{1010011} & FSGNJ.D rd,rs1,rs2 \\
 \cline{2-11}
   
@@ -1673,8 +1688,9 @@
 \multicolumn{1}{|c|}{rd} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{rs2} &
-\multicolumn{4}{c|}{0011000} &
-\multicolumn{2}{c|}{001} &
+\multicolumn{3}{c|}{00110} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{01} &
 \multicolumn{1}{c|}{1010011} & FSGNJN.D rd,rs1,rs2 \\
 \cline{2-11}
   
@@ -1683,8 +1699,9 @@
 \multicolumn{1}{|c|}{rd} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{rs2} &
-\multicolumn{4}{c|}{0011100} &
-\multicolumn{2}{c|}{001} &
+\multicolumn{3}{c|}{00111} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{01} &
 \multicolumn{1}{c|}{1010011} & FSGNJX.D rd,rs1,rs2 \\
 \cline{2-11}
   
@@ -1737,8 +1754,9 @@
 \multicolumn{1}{|c|}{rd} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{rs2} &
-\multicolumn{4}{c|}{1010100} &
-\multicolumn{2}{c|}{001} &
+\multicolumn{3}{c|}{10101} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{01} &
 \multicolumn{1}{c|}{1010011} & FEQ.D rd,rs1,rs2 \\
 \cline{2-11}
   
@@ -1747,8 +1765,9 @@
 \multicolumn{1}{|c|}{rd} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{rs2} &
-\multicolumn{4}{c|}{1011000} &
-\multicolumn{2}{c|}{001} &
+\multicolumn{3}{c|}{10110} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{01} &
 \multicolumn{1}{c|}{1010011} & FLT.D rd,rs1,rs2 \\
 \cline{2-11}
   
@@ -1757,8 +1776,9 @@
 \multicolumn{1}{|c|}{rd} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{rs2} &
-\multicolumn{4}{c|}{1011100} &
-\multicolumn{2}{c|}{001} &
+\multicolumn{3}{c|}{10111} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{01} &
 \multicolumn{1}{c|}{1010011} & FLE.D rd,rs1,rs2 \\
 \cline{2-11}
   
@@ -1766,7 +1786,7 @@
 &
 \multicolumn{10}{c}{} & \\
 &
-\multicolumn{10}{c}{\bf RV64D Instruction Subset} & \\
+\multicolumn{10}{c}{\bf RV64D Instruction Subset (in addition to RV32D)} & \\
 \cline{2-11}
   
 
@@ -1796,8 +1816,9 @@
 \multicolumn{1}{|c|}{rd} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{00000} &
-\multicolumn{4}{c|}{1111000} &
-\multicolumn{2}{c|}{001} &
+\multicolumn{3}{c|}{11110} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{01} &
 \multicolumn{1}{c|}{1010011} & FMV.D.X rd,rs1 \\
 \cline{2-11}
   
@@ -1828,8 +1849,9 @@
 \multicolumn{1}{|c|}{rd} &
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{00000} &
-\multicolumn{4}{c|}{1110000} &
-\multicolumn{2}{c|}{001} &
+\multicolumn{3}{c|}{11100} &
+\multicolumn{2}{c|}{000} &
+\multicolumn{1}{c|}{01} &
 \multicolumn{1}{c|}{1010011} & FMV.X.D rd,rs1 \\
 \cline{2-11}
   
diff --git a/parse-opcodes b/parse-opcodes
index 8c1c771..d918d40 100755
--- a/parse-opcodes
+++ b/parse-opcodes
@@ -337,11 +337,11 @@ def print_header():
 \\instbitrange{26}{22} &
 \\instbitrange{21}{17} &
 \\instbit{16} &
-\\instbit{15} &
-\\instbitrange{14}{12} &
+ &
+\\instbitrange{}{12} &
 \\instbitrange{11}{10} &
 \\instbit{9} &
-\\instbitrange{8}{7} &
+\\instbitrange{}{7} &
 \\instbitrange{6}{0} \\\\
 \\cline{2-11}
 &
@@ -422,7 +422,8 @@ def print_inst(n):
     print_r4_rm_type(n, match[n], arguments[n])
   elif 'rs3' in arguments[n]:
     print_r4_type(n, match[n], arguments[n])
-  elif 'rm' in arguments[n]:
+  elif 'rm' in arguments[n] or \
+      filter(lambda x: x in n, ['fmin','fmax','fsgnj','fmv','feq','flt','fle','mtfsr','mffsr']):
     print_r_rm_type(n, match[n], arguments[n])
   else:
     print_r_type(n, match[n], arguments[n])
@@ -444,14 +445,14 @@ def make_latex_table():
   print_footer(0)
 
   print_header()
-  print_subtitle('RV64I Instruction Subset')
+  print_subtitle('RV64I Instruction Subset (in addition to RV32I)')
   print_insts('lwu', 'ld', 'sd')
   print_insts('addiw', 'slliw', 'srliw', 'sraiw')
   print_insts('addw', 'subw', 'sllw', 'srlw', 'sraw')
   print_subtitle('RV32M Instruction Subset')
   print_insts('mul', 'mulh', 'mulhsu', 'mulhu')
   print_insts('div', 'divu', 'rem', 'remu')
-  print_subtitle('RV64M Instruction Subset')
+  print_subtitle('RV64M Instruction Subset (in addition to RV32M)')
   print_insts('mulw', 'divw', 'divuw', 'remw', 'remuw')
   print_subtitle('RV32A Instruction Subset')
   print_insts('amoadd.w', 'amoswap.w', 'amoand.w', 'amoor.w')
@@ -460,7 +461,7 @@ def make_latex_table():
   print_footer(0)
 
   print_header()
-  print_subtitle('RV64A Instruction Subset')
+  print_subtitle('RV64A Instruction Subset (in addition to RV32A)')
   print_insts('amoadd.d', 'amoswap.d', 'amoand.d', 'amoor.d')
   print_insts('amomin.d', 'amomax.d', 'amominu.d', 'amomaxu.d')
   print_insts('lr.d', 'sc.d')
@@ -469,13 +470,14 @@ def make_latex_table():
   print_insts('fadd.s', 'fsub.s', 'fmul.s', 'fdiv.s', 'fsqrt.s', 'fmin.s', 'fmax.s')
   print_insts('fmadd.s', 'fmsub.s', 'fnmsub.s', 'fnmadd.s')
   print_insts('fsgnj.s', 'fsgnjn.s', 'fsgnjx.s')
-  print_insts('fcvt.s.w', 'fcvt.s.wu', 'fmv.s.x', 'mtfsr')
-  print_insts('fcvt.w.s', 'fcvt.wu.s', 'fmv.x.s', 'mffsr')
+  print_insts('fcvt.s.w', 'fcvt.s.wu', 'fmv.s.x')
+  print_insts('fcvt.w.s', 'fcvt.wu.s', 'fmv.x.s')
   print_insts('feq.s', 'flt.s', 'fle.s')
+  print_insts('mtfsr', 'mffsr')
   print_footer(0)
 
   print_header()
-  print_subtitle('RV64F Instruction Subset')
+  print_subtitle('RV64F Instruction Subset (in addition to RV32F)')
   print_insts('fcvt.s.l', 'fcvt.s.lu')
   print_insts('fcvt.l.s', 'fcvt.lu.s')
   print_subtitle('RV32D Instruction Subset')
@@ -486,7 +488,7 @@ def make_latex_table():
   print_insts('fcvt.d.w', 'fcvt.d.wu')
   print_insts('fcvt.w.d', 'fcvt.wu.d')
   print_insts('feq.d', 'flt.d', 'fle.d')
-  print_subtitle('RV64D Instruction Subset')
+  print_subtitle('RV64D Instruction Subset (in addition to RV32D)')
   print_insts('fcvt.d.l', 'fcvt.d.lu', 'fmv.d.x')
   print_insts('fcvt.l.d', 'fcvt.lu.d', 'fmv.x.d')
   print_insts('fcvt.s.d', 'fcvt.d.s')
-- 
cgit v1.2.3