From 4ae1384438363dc00617ea73078fad8f31ee4865 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 12 Mar 2015 23:07:23 -0700 Subject: Add hcall instruction --- inst.chisel | 1 + opcodes | 1 + 2 files changed, 2 insertions(+) diff --git a/inst.chisel b/inst.chisel index a4f876b..16ed411 100644 --- a/inst.chisel +++ b/inst.chisel @@ -90,6 +90,7 @@ object Instructions { def SBREAK = Bits("b00000000000100000000000001110011") def SRET = Bits("b00010000001000000000000001110011") def SFENCE_VM = Bits("b000100000100?????000000001110011") + def HCALL = Bits("b00010000000000000000000001110011") def MCALL = Bits("b00100000000000000000000001110011") def MRET = Bits("b00110000001000000000000001110011") def MRTS = Bits("b00110000100100000000000001110011") diff --git a/opcodes b/opcodes index de4cc01..98e4a79 100644 --- a/opcodes +++ b/opcodes @@ -117,6 +117,7 @@ scall 11..7=0 19..15=0 31..20=0x000 14..12=0 6..2=0x1C 1..0=3 sbreak 11..7=0 19..15=0 31..20=0x001 14..12=0 6..2=0x1C 1..0=3 sret 11..7=0 19..15=0 31..20=0x102 14..12=0 6..2=0x1C 1..0=3 sfence.vm 11..7=0 rs1 31..20=0x104 14..12=0 6..2=0x1C 1..0=3 +hcall 11..7=0 19..15=0 31..20=0x100 14..12=0 6..2=0x1C 1..0=3 mcall 11..7=0 19..15=0 31..20=0x200 14..12=0 6..2=0x1C 1..0=3 mret 11..7=0 19..15=0 31..20=0x302 14..12=0 6..2=0x1C 1..0=3 mrts 11..7=0 19..15=0 31..20=0x309 14..12=0 6..2=0x1C 1..0=3 -- cgit v1.2.3