From 436835918e6801522f4b201b7304399e0714c6af Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Sun, 5 Jul 2015 16:48:22 -0700
Subject: New machine-mode timer facility

---
 inst.chisel   | 4 ++--
 parse-opcodes | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/inst.chisel b/inst.chisel
index 0c49d6c..f7bfd44 100644
--- a/inst.chisel
+++ b/inst.chisel
@@ -244,7 +244,6 @@ object CSRs {
   val sstatus = 0x100
   val stvec = 0x101
   val sie = 0x104
-  val stimecmp = 0x121
   val sscratch = 0x140
   val sepc = 0x141
   val sip = 0x144
@@ -283,6 +282,7 @@ object CSRs {
   val instrethw = 0x982
   val stimeh = 0xd81
   val stimehw = 0xa81
+  val mtimecmph = 0x361
   val mtimeh = 0x741
   val all = {
     val res = collection.mutable.ArrayBuffer[Int]()
@@ -312,7 +312,6 @@ object CSRs {
     res += sstatus
     res += stvec
     res += sie
-    res += stimecmp
     res += sscratch
     res += sepc
     res += sip
@@ -355,6 +354,7 @@ object CSRs {
     res += instrethw
     res += stimeh
     res += stimehw
+    res += mtimecmph
     res += mtimeh
     res.toArray
   }
diff --git a/parse-opcodes b/parse-opcodes
index d3987dd..8650acf 100755
--- a/parse-opcodes
+++ b/parse-opcodes
@@ -81,7 +81,6 @@ csrs = [
   (0x100, 'sstatus'),
   (0x101, 'stvec'),
   (0x104, 'sie'),
-  (0x121, 'stimecmp'),
   (0x140, 'sscratch'),
   (0x141, 'sepc'),
   (0x144, 'sip'),
@@ -144,6 +143,7 @@ csrs32 = [
   (0xA81, 'stimehw'),
 
   # Standard Machine R/W
+  (0x361, 'mtimecmph'),
   (0x741, 'mtimeh'),
 ]
 
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