From 1b4f2b1e85d6623e64d4348ef1a912a3033d14ea Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@eecs.berkeley.edu>
Date: Tue, 21 Jan 2014 14:42:52 -0800
Subject: Auto-generate exception cause numbers

---
 encoding.h    | 13 -------------
 inst.chisel   | 30 ++++++++++++++++++++++++++++++
 parse-opcodes | 27 +++++++++++++++++++++++++++
 3 files changed, 57 insertions(+), 13 deletions(-)

diff --git a/encoding.h b/encoding.h
index a5467e0..319b72f 100644
--- a/encoding.h
+++ b/encoding.h
@@ -26,19 +26,6 @@
 #define IMPL_SPIKE  1
 #define IMPL_ROCKET 2
 
-#define CAUSE_MISALIGNED_FETCH 0
-#define CAUSE_FAULT_FETCH 1
-#define CAUSE_ILLEGAL_INSTRUCTION 2
-#define CAUSE_PRIVILEGED_INSTRUCTION 3
-#define CAUSE_FP_DISABLED 4
-#define CAUSE_SYSCALL 6
-#define CAUSE_BREAKPOINT 7
-#define CAUSE_MISALIGNED_LOAD 8
-#define CAUSE_MISALIGNED_STORE 9
-#define CAUSE_FAULT_LOAD 10
-#define CAUSE_FAULT_STORE 11
-#define CAUSE_ACCELERATOR_DISABLED 12
-
 // page table entry (PTE) fields
 #define PTE_V    0x001 // Entry is a page Table descriptor
 #define PTE_T    0x002 // Entry is a page Table, not a terminal node
diff --git a/inst.chisel b/inst.chisel
index a805101..c1dca0b 100644
--- a/inst.chisel
+++ b/inst.chisel
@@ -180,6 +180,36 @@ object Instructions {
   def CUSTOM3_RD_RS1     = Bits("b?????????????????110?????1111011")
   def CUSTOM3_RD_RS1_RS2 = Bits("b?????????????????111?????1111011")
 }
+object Causes {
+  val misaligned_fetch = 0x0
+  val fault_fetch = 0x1
+  val illegal_instruction = 0x2
+  val privileged_instruction = 0x3
+  val fp_disabled = 0x4
+  val syscall = 0x6
+  val breakpoint = 0x7
+  val misaligned_load = 0x8
+  val misaligned_store = 0x9
+  val fault_load = 0xa
+  val fault_store = 0xb
+  val accelerator_disabled = 0xc
+  val all = {
+    val res = collection.mutable.ArrayBuffer[Int]()
+    res += misaligned_fetch
+    res += fault_fetch
+    res += illegal_instruction
+    res += privileged_instruction
+    res += fp_disabled
+    res += syscall
+    res += breakpoint
+    res += misaligned_load
+    res += misaligned_store
+    res += fault_load
+    res += fault_store
+    res += accelerator_disabled
+    res.toArray
+  }
+}
 object CSRs {
   val fflags = 0x1
   val frm = 0x2
diff --git a/parse-opcodes b/parse-opcodes
index 6c12a16..6b55d5d 100755
--- a/parse-opcodes
+++ b/parse-opcodes
@@ -40,6 +40,21 @@ arglut['cimm6'] = (15,10)
 arglut['cimm10'] = (14,5)
 arglut['cimm5'] = (9,5)
 
+causes = [
+  (0x00, 'misaligned fetch'),
+  (0x01, 'fault fetch'),
+  (0x02, 'illegal instruction'),
+  (0x03, 'privileged instruction'),
+  (0x04, 'FP disabled'),
+  (0x06, 'syscall'),
+  (0x07, 'breakpoint'),
+  (0x08, 'misaligned load'),
+  (0x09, 'misaligned store'),
+  (0x0A, 'fault load'),
+  (0x0B, 'fault store'),
+  (0x0C, 'accelerator disabled'),
+]
+
 csrs = [
   (0x001, 'fflags'),
   (0x002, 'frm'),
@@ -88,6 +103,8 @@ def make_c(match,mask):
     print '#define MASK_%s  %s' % (name2, hex(mask[name]))
   for num, name in csrs:
     print '#define CSR_%s %s' % (name.upper(), hex(num))
+  for num, name in causes:
+    print '#define CAUSE_%s %s' % (name.upper().replace(' ', '_'), hex(num))
   print '#endif'
 
   print '#ifdef DECLARE_INSN'
@@ -601,6 +618,16 @@ def make_chisel():
   for name in namelist:
     print_chisel_insn(name)
   print '}'
+  print 'object Causes {'
+  for num, name in causes:
+    print '  val %s = %s' % (name.lower().replace(' ', '_'), hex(num))
+  print '  val all = {'
+  print '    val res = collection.mutable.ArrayBuffer[Int]()'
+  for num, name in causes:
+    print '    res += %s' % (name.lower().replace(' ', '_'))
+  print '    res.toArray'
+  print '  }'
+  print '}'
   print 'object CSRs {'
   for num, name in csrs:
     print '  val %s = %s' % (name, hex(num))
-- 
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