From 05e0d24dc582a92eae1809451833d5c76335b81a Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU>
Date: Fri, 13 May 2011 14:56:57 -0700
Subject: tweaked encoding of rdcycle & cousins

---
 inst.v          |  9 ++++++---
 instr-table.tex | 42 ++++++++++++++++++++++++++++++++++++------
 opcodes         | 13 ++++++++-----
 3 files changed, 50 insertions(+), 14 deletions(-)

diff --git a/inst.v b/inst.v
index 49f712c..e67f502 100644
--- a/inst.v
+++ b/inst.v
@@ -83,6 +83,9 @@
 `define FENCE      32'b?????_?????_????????????_010_0101111
 `define SYSCALL    32'b00000_00000_00000_0000000000_1110111
 `define BREAK      32'b00000_00000_00000_0000000001_1110111
+`define RDCYCLE    32'b?????_00000_00000_0000000100_1110111
+`define RDTIME     32'b?????_00000_00000_0000001100_1110111
+`define RDINSTRET  32'b?????_00000_00000_0000010100_1110111
 `define FENCE_L_V  32'b?????_?????_????????????_100_0101111
 `define FENCE_G_V  32'b?????_?????_????????????_101_0101111
 `define FENCE_L_CV 32'b?????_?????_????????????_110_0101111
@@ -125,10 +128,10 @@
 `define FCVT_S_WU  32'b?????_?????_00000_01111_???_00_1010011
 `define FCVT_D_L   32'b?????_?????_00000_01100_???_01_1010011
 `define FCVT_D_LU  32'b?????_?????_00000_01101_???_01_1010011
-`define FCVT_D_W   32'b?????_?????_00000_01110_000_01_1010011
-`define FCVT_D_WU  32'b?????_?????_00000_01111_000_01_1010011
+`define FCVT_D_W   32'b?????_?????_00000_01110_???_01_1010011
+`define FCVT_D_WU  32'b?????_?????_00000_01111_???_01_1010011
 `define FCVT_S_D   32'b?????_?????_00000_10001_???_00_1010011
-`define FCVT_D_S   32'b?????_?????_00000_10000_000_01_1010011
+`define FCVT_D_S   32'b?????_?????_00000_10000_???_01_1010011
 `define FEQ_S      32'b?????_?????_?????_10101_000_00_1010011
 `define FLT_S      32'b?????_?????_?????_10110_000_00_1010011
 `define FLE_S      32'b?????_?????_?????_10111_000_00_1010011
diff --git a/instr-table.tex b/instr-table.tex
index a248e85..3ccc735 100644
--- a/instr-table.tex
+++ b/instr-table.tex
@@ -1518,9 +1518,9 @@
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{00000} &
 \multicolumn{3}{c|}{10000} &
-\multicolumn{2}{c|}{000} &
+\multicolumn{2}{c|}{rm} &
 \multicolumn{1}{c|}{01} &
-\multicolumn{1}{c|}{1010011} & FCVT.D.S rd,rs1 \\
+\multicolumn{1}{c|}{1010011} & FCVT.D.S rd,rs1[,rm] \\
 \cline{2-11}
   
 
@@ -1602,9 +1602,9 @@
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{00000} &
 \multicolumn{3}{c|}{01110} &
-\multicolumn{2}{c|}{000} &
+\multicolumn{2}{c|}{rm} &
 \multicolumn{1}{c|}{01} &
-\multicolumn{1}{c|}{1010011} & FCVT.D.W rd,rs1 \\
+\multicolumn{1}{c|}{1010011} & FCVT.D.W rd,rs1[,rm] \\
 \cline{2-11}
   
 
@@ -1613,9 +1613,9 @@
 \multicolumn{1}{c|}{rs1} &
 \multicolumn{1}{c|}{00000} &
 \multicolumn{3}{c|}{01111} &
-\multicolumn{2}{c|}{000} &
+\multicolumn{2}{c|}{rm} &
 \multicolumn{1}{c|}{01} &
-\multicolumn{1}{c|}{1010011} & FCVT.D.WU rd,rs1 \\
+\multicolumn{1}{c|}{1010011} & FCVT.D.WU rd,rs1[,rm] \\
 \cline{2-11}
   
 
@@ -2020,6 +2020,36 @@
 \cline{2-11}
   
 
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{4}{c|}{0000000} &
+\multicolumn{2}{c|}{100} &
+\multicolumn{1}{c|}{1110111} & RDCYCLE rd \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{4}{c|}{0000001} &
+\multicolumn{2}{c|}{100} &
+\multicolumn{1}{c|}{1110111} & RDTIME rd \\
+\cline{2-11}
+  
+
+&
+\multicolumn{1}{|c|}{rd} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{1}{c|}{00000} &
+\multicolumn{4}{c|}{0000010} &
+\multicolumn{2}{c|}{100} &
+\multicolumn{1}{c|}{1110111} & RDINSTRET rd \\
+\cline{2-11}
+  
+
 &
 \multicolumn{1}{|c|}{00000} &
 \multicolumn{1}{c|}{00000} &
diff --git a/opcodes b/opcodes
index 96d8eea..82eafc9 100644
--- a/opcodes
+++ b/opcodes
@@ -107,8 +107,11 @@ amomaxu.d    rd rs1 rs2 16..10=7 9..7=3 6..2=0x0A 1..0=3
 fence.i     rd rs1 imm12 9..7=1 6..2=0x0B 1..0=3
 fence       rd rs1 imm12 9..7=2 6..2=0x0B 1..0=3
 
-syscall 31..27=0 26..22=0 21..17=0 16..7=0 6..2=0x1D 1..0=3
-break   31..27=0 26..22=0 21..17=0 16..7=1 6..2=0x1D 1..0=3
+syscall   31..27=0 26..22=0 21..17=0 16..10=0 9..7=0 6..2=0x1D 1..0=3
+break     31..27=0 26..22=0 21..17=0 16..10=0 9..7=1 6..2=0x1D 1..0=3
+rdcycle   rd       26..22=0 21..17=0 16..10=0 9..7=4 6..2=0x1D 1..0=3
+rdtime    rd       26..22=0 21..17=0 16..10=1 9..7=4 6..2=0x1D 1..0=3
+rdinstret rd       26..22=0 21..17=0 16..10=2 9..7=4 6..2=0x1D 1..0=3
 
 # vector fence instructions
 fence.l.v   rd rs1 imm12 9..7=4 6..2=0x0B 1..0=3
@@ -164,11 +167,11 @@ fcvt.s.wu   rd rs1 21..17=0 16..12=0xF  rm      8..7=0 6..2=0x14 1..0=3
 
 fcvt.d.l    rd rs1 21..17=0 16..12=0xC  rm      8..7=1 6..2=0x14 1..0=3
 fcvt.d.lu   rd rs1 21..17=0 16..12=0xD  rm      8..7=1 6..2=0x14 1..0=3
-fcvt.d.w    rd rs1 21..17=0 16..12=0xE  11..9=0 8..7=1 6..2=0x14 1..0=3
-fcvt.d.wu   rd rs1 21..17=0 16..12=0xF  11..9=0 8..7=1 6..2=0x14 1..0=3
+fcvt.d.w    rd rs1 21..17=0 16..12=0xE  rm      8..7=1 6..2=0x14 1..0=3
+fcvt.d.wu   rd rs1 21..17=0 16..12=0xF  rm      8..7=1 6..2=0x14 1..0=3
 
 fcvt.s.d    rd rs1 21..17=0 16..14=0x4 13..12=1 rm 8..7=0 6..2=0x14 1..0=3
-fcvt.d.s    rd rs1 21..17=0 16..14=0x4 13..12=0 11..9=0 8..7=1 6..2=0x14 1..0=3
+fcvt.d.s    rd rs1 21..17=0 16..14=0x4 13..12=0 rm 8..7=1 6..2=0x14 1..0=3
 
 feq.s     rd rs1 rs2      16..12=0x15 11..9=0 8..7=0 6..2=0x14 1..0=3
 flt.s     rd rs1 rs2      16..12=0x16 11..9=0 8..7=0 6..2=0x14 1..0=3
-- 
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