riscv-opcodes - RISC-V opcodes

	Commit message (Collapse)	Author	Age
*	Factor out Hwacha/RVC and rename MFTX/MXTF to FMV	Andrew Waterman	2013-07-26
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*	Refactor parse-opcodes	Andrew Waterman	2013-07-25
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*	add auipc, lr, sc	Andrew Waterman	2013-04-17
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*	new supervisor mode	Andrew Waterman	2012-03-24
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*	change vector fence names/encoding	Andrew Waterman	2012-03-18
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*	clean up vector exception instructions	Yunsup Lee	2012-03-18
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*	add more instructions for vector exception handling	Yunsup Lee	2012-03-13
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*	add vvcfg,vtcfg	Yunsup Lee	2012-03-13
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*	opcodes cleanup	Yunsup Lee	2012-03-13
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*	slight change to vector supervisor instructions	Yunsup Lee	2012-03-10
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*	new instructions to handle vector exceptions	Yunsup Lee	2012-03-03
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*	temporary undoing of renaming	Andrew Waterman	2011-06-19
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*	Renamed packages	Andrew Waterman	2011-06-19
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*	[riscv-isa-run] code cleanup; added README	Andrew Waterman	2011-06-19
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*	[opcodes,pk,sim,xcc] resolve a conflict	Yunsup Lee	2011-05-15
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*	[libs,opcodes,pk,sim,xcc] add mov,fmov, shuffle vec insts	Yunsup Lee	2011-05-15
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*	tweaked encoding of rdcycle & cousins	Andrew Waterman	2011-05-13
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*	[opcodes] reordered RVC instructions	Andrew Waterman	2011-05-06
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*	[xcc,sim,opcodes] added c.addiw	Andrew Waterman	2011-04-24
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*	[xcc,sim,opcodes] added more RVC instructions	Andrew Waterman	2011-04-24
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*	[xcc,sim,opcodes] added rvc conditional branches	Andrew Waterman	2011-04-18
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*	[xcc,pk,sim] added privileged cflush instruction	Andrew Waterman	2011-04-12
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*	[xcc,sim] rvc loads and stores	Andrew Waterman	2011-04-12
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*	[xcc,sim,opcodes] more rvc instructions and bug fixes	Andrew Waterman	2011-04-11
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*	[xcc, sim] added rvc insn c.li; misc fixes	Andrew Waterman	2011-04-09
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*	[xcc,pk,sim,opcodes] added first RVC instruction	Andrew Waterman	2011-04-09
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*	[opcodes,pk,sim,xcc] fix utidx - add rd	Yunsup Lee	2011-04-06
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*	[opcodes,pk,sim,xcc] fix vector mem instruction format, add vector seg mem ↵	Yunsup Lee	2011-04-05
\| \| \| \|	instructions
*	[opcodes,pk,sim,xcc] add leftover vector instructions (vf, etc.)	Yunsup Lee	2011-04-04
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*	[opcodes,pk,sim,xcc] add vector mem instructions	Yunsup Lee	2011-04-04
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*	[opcodes,pk,sim,xcc] add stop,utidx instructions	Yunsup Lee	2011-04-04
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*	[opcodes,pk,sim,xcc] add fence instructions for vector unit	Yunsup Lee	2011-04-04
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*	[opcodes] minor opcode changes	Andrew Waterman	2011-03-25
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*	[sim,pk,xcc,opcodes] removed fminmag/fmaxmag	Andrew Waterman	2011-03-25
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*	[xcc,pk,opcodes,sim] updated encoding/insn names	Andrew Waterman	2011-03-25
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*	[xcc,opcodes,pk,sim] krste's re-renaming spree	Andrew Waterman	2011-02-15
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*	[xcc,sim,opcodes] removed mtflh/mffl/mffh	Andrew Waterman	2011-02-15
\| \| \| \|	in rv32 these will be replaced with loads and stores.
*	[sim,xcc,opcodes] added back mtflh.d	Andrew Waterman	2011-02-02
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*	[opcodes,pk,sim,xcc] synci now bombs whole icache	Andrew Waterman	2011-02-02
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*	[xcc,opcodes,pk,sim] cleanup to FP ISA	Andrew Waterman	2011-02-01
\| \| \| \| \| \| \|	- Added 5th rounding mode - Removed MFCR/MTCR in favor of MFFSR/MTFSR (it was the only CR...) - merged MTF.D with MTFLH.D; operation depends on RV32/RV64 mode - made MFFL.D and MFFH.D illegal in RV64
*	[opcodes] fixed verilog generation for shifts	Andrew Waterman	2011-01-31
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*	[sim,opcodes] add mulhsu instruction	Andrew Waterman	2011-01-25
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*	[opcodes,pk,sim,xcc] great renumbering of 2011, part deux	Andrew Waterman	2011-01-25
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*	[sim, pk, xcc, opcodes] great instruction renaming of 2011	Andrew Waterman	2011-01-20
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*	[opcodes, sim, xcc] made *w insns illegal in RV32	Andrew Waterman	2011-01-18
\| \| \| \|	now generic variants behave differently in RV32 and RV64.
*	[opcodes, pk, sim, xcc] removed nor, normalized macros to addi	Andrew Waterman	2011-01-17
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*	[opcodes,pk,sim,xcc] flip fields to favor little endian	Yunsup Lee	2011-01-03
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*	[opcodes, pk, sim, xcc] Tweaked FP encoding	Andrew Waterman	2010-11-21
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*	[opcodes] generate latex and verilog correctly	Andrew Waterman	2010-11-21
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*	[xcc, sim, pk, opcodes] new instruction encoding!	Andrew Waterman	2010-11-21
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