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* Add DECLARE_CAUSE macroGravatar Andrew Waterman2014-01-21
* Move microthread-specific opcodes to opcodes-hwacha-utGravatar Quan Nguyen2014-01-21
* Auto-generate exception cause numbersGravatar Andrew Waterman2014-01-21
* Merge branch 'confprec'Gravatar Quan Nguyen2014-01-20
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* | swap JAL/JALR againGravatar Andrew Waterman2014-01-13
* | New RDCYCLE encodingGravatar Andrew Waterman2013-12-09
| * Add vsetprec instructionGravatar Quan Nguyen2013-11-29
* | New privileged ISAGravatar Andrew Waterman2013-11-25
| * Merge branch 'master' into confprecGravatar Quan Nguyen2013-11-24
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| * Add line in Makefile to parse confprecGravatar Quan Nguyen2013-11-24
* | add missing imm for storesGravatar Yunsup Lee2013-11-22
* | fix slli/slliw encoding bugGravatar Yunsup Lee2013-11-21
* | changes to the instr-tableGravatar Yunsup Lee2013-10-29
| * Move half-precision opcodes to opcodes-hwacha-utGravatar Quan Nguyen2013-10-27
| * Merge branch 'master' of github.com:ucb-bar/riscv-opcodes into confprecGravatar Quan Nguyen2013-10-27
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* | add gitignoreGravatar Yunsup Lee2013-10-18
| * Add half-precision floating-point instructionsGravatar Quan Nguyen2013-10-17
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* add hwacha exception supportGravatar Yunsup Lee2013-10-17
* custom-1 opcodes are now 0x0AGravatar Yunsup Lee2013-10-17
* revamp hwacha-v3 opcodesGravatar Yunsup Lee2013-10-10
* Fix funct field in tables.Gravatar Andrew Waterman2013-09-21
* Remove old fileGravatar Andrew Waterman2013-09-21
* Update ISA encodingGravatar Andrew Waterman2013-09-21
* hwacha v3: inst format follows the new rocket accelerator extensionsGravatar Yunsup Lee2013-08-07
* Rename MTFSR/MFFSR to FSSR/FRSRGravatar Andrew Waterman2013-08-06
* Add custom opcode spaceGravatar Andrew Waterman2013-08-06
* HW ignores upper bits of fence, but SW supplies 0Gravatar Andrew Waterman2013-07-31
* Swap J and JALR encodingsGravatar Andrew Waterman2013-07-31
* change supervisor encodingGravatar Yunsup Lee2013-07-26
* tweaksGravatar Yunsup Lee2013-07-26
* Factor out Hwacha/RVC and rename MFTX/MXTF to FMVGravatar Andrew Waterman2013-07-26
* Refactor parse-opcodesGravatar Andrew Waterman2013-07-25
* Remove JALR static hintsGravatar Andrew Waterman2013-07-25
* Remove CFLUSHGravatar Andrew Waterman2013-07-23
* add auipc, lr, scGravatar Andrew Waterman2013-04-17
* new supervisor modeGravatar Andrew Waterman2012-03-24
* change vector fence names/encodingGravatar Andrew Waterman2012-03-18
* clean up vector exception instructionsGravatar Yunsup Lee2012-03-18
* add more instructions for vector exception handlingGravatar Yunsup Lee2012-03-13
* add vvcfg,vtcfgGravatar Yunsup Lee2012-03-13
* opcodes cleanupGravatar Yunsup Lee2012-03-13
* slight change to vector supervisor instructionsGravatar Yunsup Lee2012-03-10
* new instructions to handle vector exceptionsGravatar Yunsup Lee2012-03-03
* temporary undoing of renamingGravatar Andrew Waterman2011-06-19
* Renamed packagesGravatar Andrew Waterman2011-06-19
* [riscv-isa-run] code cleanup; added READMEGravatar Andrew Waterman2011-06-19
* [sim, opcodes] made sim more decoupled from opcodesGravatar Andrew Waterman2011-06-10
* [sim,opcodes] improved sim build and run performanceGravatar Andrew Waterman2011-05-29
* [opcodes,pk,sim] add more vector traps (for #banks, illegal instructions)Gravatar Yunsup Lee2011-05-18
* [opcodes,pk,sim,xcc] resolve a conflictGravatar Yunsup Lee2011-05-15