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* Fix funct field in tables.Gravatar Andrew Waterman2013-09-21
* Remove old fileGravatar Andrew Waterman2013-09-21
* Update ISA encodingGravatar Andrew Waterman2013-09-21
* hwacha v3: inst format follows the new rocket accelerator extensionsGravatar Yunsup Lee2013-08-07
* Rename MTFSR/MFFSR to FSSR/FRSRGravatar Andrew Waterman2013-08-06
* Add custom opcode spaceGravatar Andrew Waterman2013-08-06
* HW ignores upper bits of fence, but SW supplies 0Gravatar Andrew Waterman2013-07-31
* Swap J and JALR encodingsGravatar Andrew Waterman2013-07-31
* change supervisor encodingGravatar Yunsup Lee2013-07-26
* tweaksGravatar Yunsup Lee2013-07-26
* Factor out Hwacha/RVC and rename MFTX/MXTF to FMVGravatar Andrew Waterman2013-07-26
* Refactor parse-opcodesGravatar Andrew Waterman2013-07-25
* Remove JALR static hintsGravatar Andrew Waterman2013-07-25
* Remove CFLUSHGravatar Andrew Waterman2013-07-23
* add auipc, lr, scGravatar Andrew Waterman2013-04-17
* new supervisor modeGravatar Andrew Waterman2012-03-24
* change vector fence names/encodingGravatar Andrew Waterman2012-03-18
* clean up vector exception instructionsGravatar Yunsup Lee2012-03-18
* add more instructions for vector exception handlingGravatar Yunsup Lee2012-03-13
* add vvcfg,vtcfgGravatar Yunsup Lee2012-03-13
* opcodes cleanupGravatar Yunsup Lee2012-03-13
* slight change to vector supervisor instructionsGravatar Yunsup Lee2012-03-10
* new instructions to handle vector exceptionsGravatar Yunsup Lee2012-03-03
* temporary undoing of renamingGravatar Andrew Waterman2011-06-19
* Renamed packagesGravatar Andrew Waterman2011-06-19
* [riscv-isa-run] code cleanup; added READMEGravatar Andrew Waterman2011-06-19
* [sim, opcodes] made sim more decoupled from opcodesGravatar Andrew Waterman2011-06-10
* [sim,opcodes] improved sim build and run performanceGravatar Andrew Waterman2011-05-29
* [opcodes,pk,sim] add more vector traps (for #banks, illegal instructions)Gravatar Yunsup Lee2011-05-18
* [opcodes,pk,sim,xcc] resolve a conflictGravatar Yunsup Lee2011-05-15
* [libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec instsGravatar Yunsup Lee2011-05-15
* tweaked encoding of rdcycle & cousinsGravatar Andrew Waterman2011-05-13
* [opcodes] reordered RVC instructionsGravatar Andrew Waterman2011-05-06
* [xcc,sim,opcodes] added c.addiwGravatar Andrew Waterman2011-04-24
* [xcc,sim,opcodes] added more RVC instructionsGravatar Andrew Waterman2011-04-24
* [xcc,sim,opcodes] added rvc conditional branchesGravatar Andrew Waterman2011-04-18
* [xcc,pk,sim] added privileged cflush instructionGravatar Andrew Waterman2011-04-12
* [xcc,sim] rvc loads and storesGravatar Andrew Waterman2011-04-12
* [xcc,sim,opcodes] more rvc instructions and bug fixesGravatar Andrew Waterman2011-04-11
* [xcc, sim] added rvc insn c.li; misc fixesGravatar Andrew Waterman2011-04-09
* [xcc,pk,sim,opcodes] added first RVC instructionGravatar Andrew Waterman2011-04-09
* [pk,sim] fixed parse-opcodes bugGravatar Andrew Waterman2011-04-07
* [opcodes,pk,sim,xcc] fix utidx - add rdGravatar Yunsup Lee2011-04-06
* [opcodes,pk,sim,xcc] fix vector mem instruction format, add vector seg mem in...Gravatar Yunsup Lee2011-04-05
* [opcodes,pk,sim,xcc] add leftover vector instructions (vf, etc.)Gravatar Yunsup Lee2011-04-04
* [opcodes,pk,sim,xcc] add vector mem instructionsGravatar Yunsup Lee2011-04-04
* [opcodes,pk,sim,xcc] add stop,utidx instructionsGravatar Yunsup Lee2011-04-04
* [opcodes,pk,sim,xcc] add fence instructions for vector unitGravatar Yunsup Lee2011-04-04
* [opcodes] fixed up instruction tableGravatar Andrew Waterman2011-03-25
* [opcodes] minor opcode changesGravatar Andrew Waterman2011-03-25
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