diff options
| -rw-r--r-- | inst.chisel | 29 | ||||
| -rw-r--r-- | opcodes | 9 | ||||
| -rwxr-xr-x | parse-opcodes | 14 |
3 files changed, 20 insertions, 32 deletions
diff --git a/inst.chisel b/inst.chisel index 16ed411..20362d3 100644 --- a/inst.chisel +++ b/inst.chisel @@ -88,12 +88,9 @@ object Instructions { def SC_D = Bits("b00011????????????011?????0101111") def SCALL = Bits("b00000000000000000000000001110011") def SBREAK = Bits("b00000000000100000000000001110011") - def SRET = Bits("b00010000001000000000000001110011") - def SFENCE_VM = Bits("b000100000100?????000000001110011") - def HCALL = Bits("b00010000000000000000000001110011") - def MCALL = Bits("b00100000000000000000000001110011") - def MRET = Bits("b00110000001000000000000001110011") - def MRTS = Bits("b00110000100100000000000001110011") + def SRET = Bits("b00010000000000000000000001110011") + def SFENCE_VM = Bits("b000100000001?????000000001110011") + def MRTS = Bits("b00110000010100000000000001110011") def CSRRW = Bits("b?????????????????001?????1110011") def CSRRS = Bits("b?????????????????010?????1110011") def CSRRC = Bits("b?????????????????011?????1110011") @@ -191,27 +188,23 @@ object Causes { val misaligned_fetch = 0x0 val fault_fetch = 0x1 val illegal_instruction = 0x2 - val scall = 0x4 - val hcall = 0x5 - val mcall = 0x6 - val breakpoint = 0x7 - val misaligned_load = 0x8 - val fault_load = 0x9 - val misaligned_store = 0xa - val fault_store = 0xb + val misaligned_load = 0x4 + val fault_load = 0x5 + val misaligned_store = 0x6 + val fault_store = 0x7 + val ecall = 0x8 + val breakpoint = 0x9 val all = { val res = collection.mutable.ArrayBuffer[Int]() res += misaligned_fetch res += fault_fetch res += illegal_instruction - res += scall - res += hcall - res += mcall - res += breakpoint res += misaligned_load res += fault_load res += misaligned_store res += fault_store + res += ecall + res += breakpoint res.toArray } } @@ -115,12 +115,9 @@ sc.d rd rs1 rs2 aqrl 31..29=0 28..27=3 14..12=3 6..2=0x0B 1..0=3 # SYSTEM scall 11..7=0 19..15=0 31..20=0x000 14..12=0 6..2=0x1C 1..0=3 sbreak 11..7=0 19..15=0 31..20=0x001 14..12=0 6..2=0x1C 1..0=3 -sret 11..7=0 19..15=0 31..20=0x102 14..12=0 6..2=0x1C 1..0=3 -sfence.vm 11..7=0 rs1 31..20=0x104 14..12=0 6..2=0x1C 1..0=3 -hcall 11..7=0 19..15=0 31..20=0x100 14..12=0 6..2=0x1C 1..0=3 -mcall 11..7=0 19..15=0 31..20=0x200 14..12=0 6..2=0x1C 1..0=3 -mret 11..7=0 19..15=0 31..20=0x302 14..12=0 6..2=0x1C 1..0=3 -mrts 11..7=0 19..15=0 31..20=0x309 14..12=0 6..2=0x1C 1..0=3 +sret 11..7=0 19..15=0 31..20=0x100 14..12=0 6..2=0x1C 1..0=3 +sfence.vm 11..7=0 rs1 31..20=0x101 14..12=0 6..2=0x1C 1..0=3 +mrts 11..7=0 19..15=0 31..20=0x305 14..12=0 6..2=0x1C 1..0=3 csrrw rd rs1 imm12 14..12=1 6..2=0x1C 1..0=3 csrrs rd rs1 imm12 14..12=2 6..2=0x1C 1..0=3 csrrc rd rs1 imm12 14..12=3 6..2=0x1C 1..0=3 diff --git a/parse-opcodes b/parse-opcodes index 72bc44a..d7d2602 100755 --- a/parse-opcodes +++ b/parse-opcodes @@ -45,14 +45,12 @@ causes = [ (0x00, 'misaligned fetch'), (0x01, 'fault fetch'), (0x02, 'illegal instruction'), - (0x04, 'scall'), - (0x05, 'hcall'), - (0x06, 'mcall'), - (0x07, 'breakpoint'), - (0x08, 'misaligned load'), - (0x09, 'fault load'), - (0x0A, 'misaligned store'), - (0x0B, 'fault store'), + (0x04, 'misaligned load'), + (0x05, 'fault load'), + (0x06, 'misaligned store'), + (0x07, 'fault store'), + (0x08, 'ecall'), + (0x09, 'breakpoint'), ] csrs = [ |