Remove automatically-generated files

3 files changed, 2 insertions, 2391 deletions

diff --git a/.gitignore b/.gitignore
index a01ee28..72c1533 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1 +1,3 @@
 .*.swp
+inst.chisel
+instr-table.tex
diff --git a/inst.chisel b/inst.chisel
deleted file mode 100644
index f7bfd44..0000000
--- a/inst.chisel
+++ /dev/null
@@ -1,361 +0,0 @@
-/* Automatically generated by parse-opcodes */
-object Instructions {
-  def BEQ                = Bits("b?????????????????000?????1100011")
-  def BNE                = Bits("b?????????????????001?????1100011")
-  def BLT                = Bits("b?????????????????100?????1100011")
-  def BGE                = Bits("b?????????????????101?????1100011")
-  def BLTU               = Bits("b?????????????????110?????1100011")
-  def BGEU               = Bits("b?????????????????111?????1100011")
-  def JALR               = Bits("b?????????????????000?????1100111")
-  def JAL                = Bits("b?????????????????????????1101111")
-  def LUI                = Bits("b?????????????????????????0110111")
-  def AUIPC              = Bits("b?????????????????????????0010111")
-  def ADDI               = Bits("b?????????????????000?????0010011")
-  def SLLI               = Bits("b000000???????????001?????0010011")
-  def SLTI               = Bits("b?????????????????010?????0010011")
-  def SLTIU              = Bits("b?????????????????011?????0010011")
-  def XORI               = Bits("b?????????????????100?????0010011")
-  def SRLI               = Bits("b000000???????????101?????0010011")
-  def SRAI               = Bits("b010000???????????101?????0010011")
-  def ORI                = Bits("b?????????????????110?????0010011")
-  def ANDI               = Bits("b?????????????????111?????0010011")
-  def ADD                = Bits("b0000000??????????000?????0110011")
-  def SUB                = Bits("b0100000??????????000?????0110011")
-  def SLL                = Bits("b0000000??????????001?????0110011")
-  def SLT                = Bits("b0000000??????????010?????0110011")
-  def SLTU               = Bits("b0000000??????????011?????0110011")
-  def XOR                = Bits("b0000000??????????100?????0110011")
-  def SRL                = Bits("b0000000??????????101?????0110011")
-  def SRA                = Bits("b0100000??????????101?????0110011")
-  def OR                 = Bits("b0000000??????????110?????0110011")
-  def AND                = Bits("b0000000??????????111?????0110011")
-  def ADDIW              = Bits("b?????????????????000?????0011011")
-  def SLLIW              = Bits("b0000000??????????001?????0011011")
-  def SRLIW              = Bits("b0000000??????????101?????0011011")
-  def SRAIW              = Bits("b0100000??????????101?????0011011")
-  def ADDW               = Bits("b0000000??????????000?????0111011")
-  def SUBW               = Bits("b0100000??????????000?????0111011")
-  def SLLW               = Bits("b0000000??????????001?????0111011")
-  def SRLW               = Bits("b0000000??????????101?????0111011")
-  def SRAW               = Bits("b0100000??????????101?????0111011")
-  def LB                 = Bits("b?????????????????000?????0000011")
-  def LH                 = Bits("b?????????????????001?????0000011")
-  def LW                 = Bits("b?????????????????010?????0000011")
-  def LD                 = Bits("b?????????????????011?????0000011")
-  def LBU                = Bits("b?????????????????100?????0000011")
-  def LHU                = Bits("b?????????????????101?????0000011")
-  def LWU                = Bits("b?????????????????110?????0000011")
-  def SB                 = Bits("b?????????????????000?????0100011")
-  def SH                 = Bits("b?????????????????001?????0100011")
-  def SW                 = Bits("b?????????????????010?????0100011")
-  def SD                 = Bits("b?????????????????011?????0100011")
-  def FENCE              = Bits("b?????????????????000?????0001111")
-  def FENCE_I            = Bits("b?????????????????001?????0001111")
-  def MUL                = Bits("b0000001??????????000?????0110011")
-  def MULH               = Bits("b0000001??????????001?????0110011")
-  def MULHSU             = Bits("b0000001??????????010?????0110011")
-  def MULHU              = Bits("b0000001??????????011?????0110011")
-  def DIV                = Bits("b0000001??????????100?????0110011")
-  def DIVU               = Bits("b0000001??????????101?????0110011")
-  def REM                = Bits("b0000001??????????110?????0110011")
-  def REMU               = Bits("b0000001??????????111?????0110011")
-  def MULW               = Bits("b0000001??????????000?????0111011")
-  def DIVW               = Bits("b0000001??????????100?????0111011")
-  def DIVUW              = Bits("b0000001??????????101?????0111011")
-  def REMW               = Bits("b0000001??????????110?????0111011")
-  def REMUW              = Bits("b0000001??????????111?????0111011")
-  def AMOADD_W           = Bits("b00000????????????010?????0101111")
-  def AMOXOR_W           = Bits("b00100????????????010?????0101111")
-  def AMOOR_W            = Bits("b01000????????????010?????0101111")
-  def AMOAND_W           = Bits("b01100????????????010?????0101111")
-  def AMOMIN_W           = Bits("b10000????????????010?????0101111")
-  def AMOMAX_W           = Bits("b10100????????????010?????0101111")
-  def AMOMINU_W          = Bits("b11000????????????010?????0101111")
-  def AMOMAXU_W          = Bits("b11100????????????010?????0101111")
-  def AMOSWAP_W          = Bits("b00001????????????010?????0101111")
-  def LR_W               = Bits("b00010??00000?????010?????0101111")
-  def SC_W               = Bits("b00011????????????010?????0101111")
-  def AMOADD_D           = Bits("b00000????????????011?????0101111")
-  def AMOXOR_D           = Bits("b00100????????????011?????0101111")
-  def AMOOR_D            = Bits("b01000????????????011?????0101111")
-  def AMOAND_D           = Bits("b01100????????????011?????0101111")
-  def AMOMIN_D           = Bits("b10000????????????011?????0101111")
-  def AMOMAX_D           = Bits("b10100????????????011?????0101111")
-  def AMOMINU_D          = Bits("b11000????????????011?????0101111")
-  def AMOMAXU_D          = Bits("b11100????????????011?????0101111")
-  def AMOSWAP_D          = Bits("b00001????????????011?????0101111")
-  def LR_D               = Bits("b00010??00000?????011?????0101111")
-  def SC_D               = Bits("b00011????????????011?????0101111")
-  def SCALL              = Bits("b00000000000000000000000001110011")
-  def SBREAK             = Bits("b00000000000100000000000001110011")
-  def SRET               = Bits("b00010000000000000000000001110011")
-  def SFENCE_VM          = Bits("b000100000001?????000000001110011")
-  def WFI                = Bits("b00010000001000000000000001110011")
-  def MRTH               = Bits("b00110000011000000000000001110011")
-  def MRTS               = Bits("b00110000010100000000000001110011")
-  def HRTS               = Bits("b00100000010100000000000001110011")
-  def CSRRW              = Bits("b?????????????????001?????1110011")
-  def CSRRS              = Bits("b?????????????????010?????1110011")
-  def CSRRC              = Bits("b?????????????????011?????1110011")
-  def CSRRWI             = Bits("b?????????????????101?????1110011")
-  def CSRRSI             = Bits("b?????????????????110?????1110011")
-  def CSRRCI             = Bits("b?????????????????111?????1110011")
-  def FADD_S             = Bits("b0000000??????????????????1010011")
-  def FSUB_S             = Bits("b0000100??????????????????1010011")
-  def FMUL_S             = Bits("b0001000??????????????????1010011")
-  def FDIV_S             = Bits("b0001100??????????????????1010011")
-  def FSGNJ_S            = Bits("b0010000??????????000?????1010011")
-  def FSGNJN_S           = Bits("b0010000??????????001?????1010011")
-  def FSGNJX_S           = Bits("b0010000??????????010?????1010011")
-  def FMIN_S             = Bits("b0010100??????????000?????1010011")
-  def FMAX_S             = Bits("b0010100??????????001?????1010011")
-  def FSQRT_S            = Bits("b010110000000?????????????1010011")
-  def FADD_D             = Bits("b0000001??????????????????1010011")
-  def FSUB_D             = Bits("b0000101??????????????????1010011")
-  def FMUL_D             = Bits("b0001001??????????????????1010011")
-  def FDIV_D             = Bits("b0001101??????????????????1010011")
-  def FSGNJ_D            = Bits("b0010001??????????000?????1010011")
-  def FSGNJN_D           = Bits("b0010001??????????001?????1010011")
-  def FSGNJX_D           = Bits("b0010001??????????010?????1010011")
-  def FMIN_D             = Bits("b0010101??????????000?????1010011")
-  def FMAX_D             = Bits("b0010101??????????001?????1010011")
-  def FCVT_S_D           = Bits("b010000000001?????????????1010011")
-  def FCVT_D_S           = Bits("b010000100000?????????????1010011")
-  def FSQRT_D            = Bits("b010110100000?????????????1010011")
-  def FLE_S              = Bits("b1010000??????????000?????1010011")
-  def FLT_S              = Bits("b1010000??????????001?????1010011")
-  def FEQ_S              = Bits("b1010000??????????010?????1010011")
-  def FLE_D              = Bits("b1010001??????????000?????1010011")
-  def FLT_D              = Bits("b1010001??????????001?????1010011")
-  def FEQ_D              = Bits("b1010001??????????010?????1010011")
-  def FCVT_W_S           = Bits("b110000000000?????????????1010011")
-  def FCVT_WU_S          = Bits("b110000000001?????????????1010011")
-  def FCVT_L_S           = Bits("b110000000010?????????????1010011")
-  def FCVT_LU_S          = Bits("b110000000011?????????????1010011")
-  def FMV_X_S            = Bits("b111000000000?????000?????1010011")
-  def FCLASS_S           = Bits("b111000000000?????001?????1010011")
-  def FCVT_W_D           = Bits("b110000100000?????????????1010011")
-  def FCVT_WU_D          = Bits("b110000100001?????????????1010011")
-  def FCVT_L_D           = Bits("b110000100010?????????????1010011")
-  def FCVT_LU_D          = Bits("b110000100011?????????????1010011")
-  def FMV_X_D            = Bits("b111000100000?????000?????1010011")
-  def FCLASS_D           = Bits("b111000100000?????001?????1010011")
-  def FCVT_S_W           = Bits("b110100000000?????????????1010011")
-  def FCVT_S_WU          = Bits("b110100000001?????????????1010011")
-  def FCVT_S_L           = Bits("b110100000010?????????????1010011")
-  def FCVT_S_LU          = Bits("b110100000011?????????????1010011")
-  def FMV_S_X            = Bits("b111100000000?????000?????1010011")
-  def FCVT_D_W           = Bits("b110100100000?????????????1010011")
-  def FCVT_D_WU          = Bits("b110100100001?????????????1010011")
-  def FCVT_D_L           = Bits("b110100100010?????????????1010011")
-  def FCVT_D_LU          = Bits("b110100100011?????????????1010011")
-  def FMV_D_X            = Bits("b111100100000?????000?????1010011")
-  def FLW                = Bits("b?????????????????010?????0000111")
-  def FLD                = Bits("b?????????????????011?????0000111")
-  def FSW                = Bits("b?????????????????010?????0100111")
-  def FSD                = Bits("b?????????????????011?????0100111")
-  def FMADD_S            = Bits("b?????00??????????????????1000011")
-  def FMSUB_S            = Bits("b?????00??????????????????1000111")
-  def FNMSUB_S           = Bits("b?????00??????????????????1001011")
-  def FNMADD_S           = Bits("b?????00??????????????????1001111")
-  def FMADD_D            = Bits("b?????01??????????????????1000011")
-  def FMSUB_D            = Bits("b?????01??????????????????1000111")
-  def FNMSUB_D           = Bits("b?????01??????????????????1001011")
-  def FNMADD_D           = Bits("b?????01??????????????????1001111")
-  def CUSTOM0            = Bits("b?????????????????000?????0001011")
-  def CUSTOM0_RS1        = Bits("b?????????????????010?????0001011")
-  def CUSTOM0_RS1_RS2    = Bits("b?????????????????011?????0001011")
-  def CUSTOM0_RD         = Bits("b?????????????????100?????0001011")
-  def CUSTOM0_RD_RS1     = Bits("b?????????????????110?????0001011")
-  def CUSTOM0_RD_RS1_RS2 = Bits("b?????????????????111?????0001011")
-  def CUSTOM1            = Bits("b?????????????????000?????0101011")
-  def CUSTOM1_RS1        = Bits("b?????????????????010?????0101011")
-  def CUSTOM1_RS1_RS2    = Bits("b?????????????????011?????0101011")
-  def CUSTOM1_RD         = Bits("b?????????????????100?????0101011")
-  def CUSTOM1_RD_RS1     = Bits("b?????????????????110?????0101011")
-  def CUSTOM1_RD_RS1_RS2 = Bits("b?????????????????111?????0101011")
-  def CUSTOM2            = Bits("b?????????????????000?????1011011")
-  def CUSTOM2_RS1        = Bits("b?????????????????010?????1011011")
-  def CUSTOM2_RS1_RS2    = Bits("b?????????????????011?????1011011")
-  def CUSTOM2_RD         = Bits("b?????????????????100?????1011011")
-  def CUSTOM2_RD_RS1     = Bits("b?????????????????110?????1011011")
-  def CUSTOM2_RD_RS1_RS2 = Bits("b?????????????????111?????1011011")
-  def CUSTOM3            = Bits("b?????????????????000?????1111011")
-  def CUSTOM3_RS1        = Bits("b?????????????????010?????1111011")
-  def CUSTOM3_RS1_RS2    = Bits("b?????????????????011?????1111011")
-  def CUSTOM3_RD         = Bits("b?????????????????100?????1111011")
-  def CUSTOM3_RD_RS1     = Bits("b?????????????????110?????1111011")
-  def CUSTOM3_RD_RS1_RS2 = Bits("b?????????????????111?????1111011")
-}
-object Causes {
-  val misaligned_fetch = 0x0
-  val fault_fetch = 0x1
-  val illegal_instruction = 0x2
-  val breakpoint = 0x3
-  val misaligned_load = 0x4
-  val fault_load = 0x5
-  val misaligned_store = 0x6
-  val fault_store = 0x7
-  val user_ecall = 0x8
-  val supervisor_ecall = 0x9
-  val hypervisor_ecall = 0xa
-  val machine_ecall = 0xb
-  val all = {
-    val res = collection.mutable.ArrayBuffer[Int]()
-    res += misaligned_fetch
-    res += fault_fetch
-    res += illegal_instruction
-    res += breakpoint
-    res += misaligned_load
-    res += fault_load
-    res += misaligned_store
-    res += fault_store
-    res += user_ecall
-    res += supervisor_ecall
-    res += hypervisor_ecall
-    res += machine_ecall
-    res.toArray
-  }
-}
-object CSRs {
-  val fflags = 0x1
-  val frm = 0x2
-  val fcsr = 0x3
-  val cycle = 0xc00
-  val time = 0xc01
-  val instret = 0xc02
-  val stats = 0xc0
-  val uarch0 = 0xcc0
-  val uarch1 = 0xcc1
-  val uarch2 = 0xcc2
-  val uarch3 = 0xcc3
-  val uarch4 = 0xcc4
-  val uarch5 = 0xcc5
-  val uarch6 = 0xcc6
-  val uarch7 = 0xcc7
-  val uarch8 = 0xcc8
-  val uarch9 = 0xcc9
-  val uarch10 = 0xcca
-  val uarch11 = 0xccb
-  val uarch12 = 0xccc
-  val uarch13 = 0xccd
-  val uarch14 = 0xcce
-  val uarch15 = 0xccf
-  val sstatus = 0x100
-  val stvec = 0x101
-  val sie = 0x104
-  val sscratch = 0x140
-  val sepc = 0x141
-  val sip = 0x144
-  val sptbr = 0x180
-  val sasid = 0x181
-  val cyclew = 0x900
-  val timew = 0x901
-  val instretw = 0x902
-  val stime = 0xd01
-  val scause = 0xd42
-  val sbadaddr = 0xd43
-  val stimew = 0xa01
-  val mstatus = 0x300
-  val mtvec = 0x301
-  val mtdeleg = 0x302
-  val mie = 0x304
-  val mtimecmp = 0x321
-  val mscratch = 0x340
-  val mepc = 0x341
-  val mcause = 0x342
-  val mbadaddr = 0x343
-  val mip = 0x344
-  val mtime = 0x701
-  val mcpuid = 0xf00
-  val mimpid = 0xf01
-  val mhartid = 0xf10
-  val mtohost = 0x780
-  val mfromhost = 0x781
-  val mreset = 0x782
-  val send_ipi = 0x783
-  val cycleh = 0xc80
-  val timeh = 0xc81
-  val instreth = 0xc82
-  val cyclehw = 0x980
-  val timehw = 0x981
-  val instrethw = 0x982
-  val stimeh = 0xd81
-  val stimehw = 0xa81
-  val mtimecmph = 0x361
-  val mtimeh = 0x741
-  val all = {
-    val res = collection.mutable.ArrayBuffer[Int]()
-    res += fflags
-    res += frm
-    res += fcsr
-    res += cycle
-    res += time
-    res += instret
-    res += stats
-    res += uarch0
-    res += uarch1
-    res += uarch2
-    res += uarch3
-    res += uarch4
-    res += uarch5
-    res += uarch6
-    res += uarch7
-    res += uarch8
-    res += uarch9
-    res += uarch10
-    res += uarch11
-    res += uarch12
-    res += uarch13
-    res += uarch14
-    res += uarch15
-    res += sstatus
-    res += stvec
-    res += sie
-    res += sscratch
-    res += sepc
-    res += sip
-    res += sptbr
-    res += sasid
-    res += cyclew
-    res += timew
-    res += instretw
-    res += stime
-    res += scause
-    res += sbadaddr
-    res += stimew
-    res += mstatus
-    res += mtvec
-    res += mtdeleg
-    res += mie
-    res += mtimecmp
-    res += mscratch
-    res += mepc
-    res += mcause
-    res += mbadaddr
-    res += mip
-    res += mtime
-    res += mcpuid
-    res += mimpid
-    res += mhartid
-    res += mtohost
-    res += mfromhost
-    res += mreset
-    res += send_ipi
-    res.toArray
-  }
-  val all32 = {
-    val res = collection.mutable.ArrayBuffer(all:_*)
-    res += cycleh
-    res += timeh
-    res += instreth
-    res += cyclehw
-    res += timehw
-    res += instrethw
-    res += stimeh
-    res += stimehw
-    res += mtimecmph
-    res += mtimeh
-    res.toArray
-  }
-}
diff --git a/instr-table.tex b/instr-table.tex
deleted file mode 100644
index bb5fe1b..0000000
--- a/instr-table.tex
+++ /dev/null
@@ -1,2030 +0,0 @@
-
-\newpage
-
-\begin{table}[p]
-\begin{small}
-\begin{center}
-\begin{tabular}{p{0in}p{0.4in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.4in}p{0.6in}p{0.4in}p{0.6in}p{0.7in}l}
-& & & & & & & & & & \\
-                      &
-\multicolumn{1}{l}{\instbit{31}} &
-\multicolumn{1}{r}{\instbit{27}} &
-\instbit{26} &
-\instbit{25} &
-\multicolumn{1}{l}{\instbit{24}} &
-\multicolumn{1}{r}{\instbit{20}} &
-\instbitrange{19}{15} &
-\instbitrange{14}{12} &
-\instbitrange{11}{7} &
-\instbitrange{6}{0} \\
-\cline{2-11}
-
-
-&
-\multicolumn{4}{|c|}{funct7} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{funct3} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{opcode} & R-type \\
-\cline{2-11}
-
-
-&
-\multicolumn{6}{|c|}{imm[11:0]} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{funct3} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{opcode} & I-type \\
-\cline{2-11}
-
-
-&
-\multicolumn{4}{|c|}{imm[11:5]} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{funct3} &
-\multicolumn{1}{c|}{imm[4:0]} &
-\multicolumn{1}{c|}{opcode} & S-type \\
-\cline{2-11}
-
-
-&
-\multicolumn{4}{|c|}{imm[12$\vert$10:5]} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{funct3} &
-\multicolumn{1}{c|}{imm[4:1$\vert$11]} &
-\multicolumn{1}{c|}{opcode} & SB-type \\
-\cline{2-11}
-
-
-&
-\multicolumn{8}{|c|}{imm[31:12]} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{opcode} & U-type \\
-\cline{2-11}
-
-
-&
-\multicolumn{8}{|c|}{imm[20$\vert$10:1$\vert$11$\vert$19:12]} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{opcode} & UJ-type \\
-\cline{2-11}
-
-
-&
-\multicolumn{10}{c}{} & \\
-&
-\multicolumn{10}{c}{\bf RV32I Base Instruction Set} & \\
-\cline{2-11}
-  
-
-&
-\multicolumn{8}{|c|}{imm[31:12]} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0110111} & LUI rd,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{8}{|c|}{imm[31:12]} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0010111} & AUIPC rd,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{8}{|c|}{imm[20$\vert$10:1$\vert$11$\vert$19:12]} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1101111} & JAL rd,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{imm[11:0]} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{000} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1100111} & JALR rd,rs1,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{imm[12$\vert$10:5]} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{000} &
-\multicolumn{1}{c|}{imm[4:1$\vert$11]} &
-\multicolumn{1}{c|}{1100011} & BEQ rs1,rs2,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{imm[12$\vert$10:5]} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{001} &
-\multicolumn{1}{c|}{imm[4:1$\vert$11]} &
-\multicolumn{1}{c|}{1100011} & BNE rs1,rs2,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{imm[12$\vert$10:5]} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{100} &
-\multicolumn{1}{c|}{imm[4:1$\vert$11]} &
-\multicolumn{1}{c|}{1100011} & BLT rs1,rs2,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{imm[12$\vert$10:5]} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{101} &
-\multicolumn{1}{c|}{imm[4:1$\vert$11]} &
-\multicolumn{1}{c|}{1100011} & BGE rs1,rs2,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{imm[12$\vert$10:5]} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{110} &
-\multicolumn{1}{c|}{imm[4:1$\vert$11]} &
-\multicolumn{1}{c|}{1100011} & BLTU rs1,rs2,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{imm[12$\vert$10:5]} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{111} &
-\multicolumn{1}{c|}{imm[4:1$\vert$11]} &
-\multicolumn{1}{c|}{1100011} & BGEU rs1,rs2,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{imm[11:0]} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{000} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0000011} & LB rd,rs1,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{imm[11:0]} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{001} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0000011} & LH rd,rs1,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{imm[11:0]} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0000011} & LW rd,rs1,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{imm[11:0]} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{100} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0000011} & LBU rd,rs1,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{imm[11:0]} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{101} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0000011} & LHU rd,rs1,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{imm[11:5]} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{000} &
-\multicolumn{1}{c|}{imm[4:0]} &
-\multicolumn{1}{c|}{0100011} & SB rs1,rs2,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{imm[11:5]} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{001} &
-\multicolumn{1}{c|}{imm[4:0]} &
-\multicolumn{1}{c|}{0100011} & SH rs1,rs2,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{imm[11:5]} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{imm[4:0]} &
-\multicolumn{1}{c|}{0100011} & SW rs1,rs2,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{imm[11:0]} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{000} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0010011} & ADDI rd,rs1,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{imm[11:0]} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0010011} & SLTI rd,rs1,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{imm[11:0]} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{011} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0010011} & SLTIU rd,rs1,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{imm[11:0]} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{100} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0010011} & XORI rd,rs1,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{imm[11:0]} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{110} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0010011} & ORI rd,rs1,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{imm[11:0]} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{111} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0010011} & ANDI rd,rs1,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{shamt} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{001} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0010011} & SLLI rd,rs1,shamt \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{shamt} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{101} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0010011} & SRLI rd,rs1,shamt \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0100000} &
-\multicolumn{2}{c|}{shamt} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{101} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0010011} & SRAI rd,rs1,shamt \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{000} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0110011} & ADD rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0100000} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{000} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0110011} & SUB rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{001} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0110011} & SLL rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0110011} & SLT rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{011} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0110011} & SLTU rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{100} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0110011} & XOR rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{101} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0110011} & SRL rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0100000} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{101} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0110011} & SRA rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{110} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0110011} & OR rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{111} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0110011} & AND rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{0000} &
-\multicolumn{3}{c|}{pred} &
-\multicolumn{1}{c|}{succ} &
-\multicolumn{1}{c|}{00000} &
-\multicolumn{1}{c|}{000} &
-\multicolumn{1}{c|}{00000} &
-\multicolumn{1}{c|}{0001111} & FENCE  \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{0000} &
-\multicolumn{3}{c|}{0000} &
-\multicolumn{1}{c|}{0000} &
-\multicolumn{1}{c|}{00000} &
-\multicolumn{1}{c|}{001} &
-\multicolumn{1}{c|}{00000} &
-\multicolumn{1}{c|}{0001111} & FENCE.I  \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{000000000000} &
-\multicolumn{1}{c|}{00000} &
-\multicolumn{1}{c|}{000} &
-\multicolumn{1}{c|}{00000} &
-\multicolumn{1}{c|}{1110011} & SCALL  \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{000000000001} &
-\multicolumn{1}{c|}{00000} &
-\multicolumn{1}{c|}{000} &
-\multicolumn{1}{c|}{00000} &
-\multicolumn{1}{c|}{1110011} & SBREAK  \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{110000000000} &
-\multicolumn{1}{c|}{00000} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1110011} & RDCYCLE rd \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{110010000000} &
-\multicolumn{1}{c|}{00000} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1110011} & RDCYCLEH rd \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{110000000001} &
-\multicolumn{1}{c|}{00000} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1110011} & RDTIME rd \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{110010000001} &
-\multicolumn{1}{c|}{00000} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1110011} & RDTIMEH rd \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{110000000010} &
-\multicolumn{1}{c|}{00000} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1110011} & RDINSTRET rd \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{110010000010} &
-\multicolumn{1}{c|}{00000} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1110011} & RDINSTRETH rd \\
-\cline{2-11}
-  
-
-\end{tabular}
-\end{center}
-\end{small}
-
-\label{instr-table}
-\end{table}
-  
-
-\newpage
-
-\begin{table}[p]
-\begin{small}
-\begin{center}
-\begin{tabular}{p{0in}p{0.4in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.4in}p{0.6in}p{0.4in}p{0.6in}p{0.7in}l}
-& & & & & & & & & & \\
-                      &
-\multicolumn{1}{l}{\instbit{31}} &
-\multicolumn{1}{r}{\instbit{27}} &
-\instbit{26} &
-\instbit{25} &
-\multicolumn{1}{l}{\instbit{24}} &
-\multicolumn{1}{r}{\instbit{20}} &
-\instbitrange{19}{15} &
-\instbitrange{14}{12} &
-\instbitrange{11}{7} &
-\instbitrange{6}{0} \\
-\cline{2-11}
-
-
-&
-\multicolumn{4}{|c|}{funct7} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{funct3} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{opcode} & R-type \\
-\cline{2-11}
-
-
-&
-\multicolumn{6}{|c|}{imm[11:0]} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{funct3} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{opcode} & I-type \\
-\cline{2-11}
-
-
-&
-\multicolumn{4}{|c|}{imm[11:5]} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{funct3} &
-\multicolumn{1}{c|}{imm[4:0]} &
-\multicolumn{1}{c|}{opcode} & S-type \\
-\cline{2-11}
-
-
-&
-\multicolumn{10}{c}{} & \\
-&
-\multicolumn{10}{c}{\bf RV64I Base Instruction Set (in addition to RV32I)} & \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{imm[11:0]} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{110} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0000011} & LWU rd,rs1,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{imm[11:0]} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{011} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0000011} & LD rd,rs1,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{imm[11:5]} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{011} &
-\multicolumn{1}{c|}{imm[4:0]} &
-\multicolumn{1}{c|}{0100011} & SD rs1,rs2,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{3}{|c|}{000000} &
-\multicolumn{3}{c|}{shamt} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{001} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0010011} & SLLI rd,rs1,shamt \\
-\cline{2-11}
-  
-
-&
-\multicolumn{3}{|c|}{000000} &
-\multicolumn{3}{c|}{shamt} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{101} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0010011} & SRLI rd,rs1,shamt \\
-\cline{2-11}
-  
-
-&
-\multicolumn{3}{|c|}{010000} &
-\multicolumn{3}{c|}{shamt} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{101} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0010011} & SRAI rd,rs1,shamt \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{imm[11:0]} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{000} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0011011} & ADDIW rd,rs1,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{shamt} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{001} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0011011} & SLLIW rd,rs1,shamt \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{shamt} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{101} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0011011} & SRLIW rd,rs1,shamt \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0100000} &
-\multicolumn{2}{c|}{shamt} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{101} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0011011} & SRAIW rd,rs1,shamt \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{000} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0111011} & ADDW rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0100000} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{000} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0111011} & SUBW rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{001} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0111011} & SLLW rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{101} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0111011} & SRLW rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0100000} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{101} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0111011} & SRAW rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{10}{c}{} & \\
-&
-\multicolumn{10}{c}{\bf RV32M Standard Extension} & \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000001} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{000} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0110011} & MUL rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000001} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{001} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0110011} & MULH rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000001} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0110011} & MULHSU rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000001} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{011} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0110011} & MULHU rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000001} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{100} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0110011} & DIV rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000001} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{101} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0110011} & DIVU rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000001} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{110} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0110011} & REM rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000001} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{111} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0110011} & REMU rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{10}{c}{} & \\
-&
-\multicolumn{10}{c}{\bf RV64M Standard Extension (in addition to RV32M)} & \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000001} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{000} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0111011} & MULW rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000001} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{100} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0111011} & DIVW rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000001} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{101} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0111011} & DIVUW rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000001} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{110} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0111011} & REMW rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000001} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{111} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0111011} & REMUW rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{10}{c}{} & \\
-&
-\multicolumn{10}{c}{\bf RV32A Standard Extension} & \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{00010} &
-\multicolumn{1}{c|}{aq} &
-\multicolumn{1}{c|}{rl} &
-\multicolumn{2}{c|}{00000} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0101111} & LR.W rd,rs1 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{00011} &
-\multicolumn{1}{c|}{aq} &
-\multicolumn{1}{c|}{rl} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0101111} & SC.W rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{00001} &
-\multicolumn{1}{c|}{aq} &
-\multicolumn{1}{c|}{rl} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0101111} & AMOSWAP.W rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{00000} &
-\multicolumn{1}{c|}{aq} &
-\multicolumn{1}{c|}{rl} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0101111} & AMOADD.W rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{00100} &
-\multicolumn{1}{c|}{aq} &
-\multicolumn{1}{c|}{rl} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0101111} & AMOXOR.W rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{01100} &
-\multicolumn{1}{c|}{aq} &
-\multicolumn{1}{c|}{rl} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0101111} & AMOAND.W rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{01000} &
-\multicolumn{1}{c|}{aq} &
-\multicolumn{1}{c|}{rl} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0101111} & AMOOR.W rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{10000} &
-\multicolumn{1}{c|}{aq} &
-\multicolumn{1}{c|}{rl} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0101111} & AMOMIN.W rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{10100} &
-\multicolumn{1}{c|}{aq} &
-\multicolumn{1}{c|}{rl} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0101111} & AMOMAX.W rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{11000} &
-\multicolumn{1}{c|}{aq} &
-\multicolumn{1}{c|}{rl} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0101111} & AMOMINU.W rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{11100} &
-\multicolumn{1}{c|}{aq} &
-\multicolumn{1}{c|}{rl} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0101111} & AMOMAXU.W rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-\end{tabular}
-\end{center}
-\end{small}
-
-\label{instr-table}
-\end{table}
-  
-
-\newpage
-
-\begin{table}[p]
-\begin{small}
-\begin{center}
-\begin{tabular}{p{0in}p{0.4in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.4in}p{0.6in}p{0.4in}p{0.6in}p{0.7in}l}
-& & & & & & & & & & \\
-                      &
-\multicolumn{1}{l}{\instbit{31}} &
-\multicolumn{1}{r}{\instbit{27}} &
-\instbit{26} &
-\instbit{25} &
-\multicolumn{1}{l}{\instbit{24}} &
-\multicolumn{1}{r}{\instbit{20}} &
-\instbitrange{19}{15} &
-\instbitrange{14}{12} &
-\instbitrange{11}{7} &
-\instbitrange{6}{0} \\
-\cline{2-11}
-
-
-&
-\multicolumn{4}{|c|}{funct7} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{funct3} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{opcode} & R-type \\
-\cline{2-11}
-
-
-&
-\multicolumn{2}{|c|}{rs3} &
-\multicolumn{2}{c|}{funct2} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{funct3} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{opcode} & R4-type \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{imm[11:0]} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{funct3} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{opcode} & I-type \\
-\cline{2-11}
-
-
-&
-\multicolumn{4}{|c|}{imm[11:5]} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{funct3} &
-\multicolumn{1}{c|}{imm[4:0]} &
-\multicolumn{1}{c|}{opcode} & S-type \\
-\cline{2-11}
-
-
-&
-\multicolumn{10}{c}{} & \\
-&
-\multicolumn{10}{c}{\bf RV64A Standard Extension (in addition to RV32A)} & \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{00010} &
-\multicolumn{1}{c|}{aq} &
-\multicolumn{1}{c|}{rl} &
-\multicolumn{2}{c|}{00000} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{011} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0101111} & LR.D rd,rs1 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{00011} &
-\multicolumn{1}{c|}{aq} &
-\multicolumn{1}{c|}{rl} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{011} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0101111} & SC.D rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{00001} &
-\multicolumn{1}{c|}{aq} &
-\multicolumn{1}{c|}{rl} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{011} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0101111} & AMOSWAP.D rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{00000} &
-\multicolumn{1}{c|}{aq} &
-\multicolumn{1}{c|}{rl} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{011} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0101111} & AMOADD.D rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{00100} &
-\multicolumn{1}{c|}{aq} &
-\multicolumn{1}{c|}{rl} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{011} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0101111} & AMOXOR.D rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{01100} &
-\multicolumn{1}{c|}{aq} &
-\multicolumn{1}{c|}{rl} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{011} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0101111} & AMOAND.D rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{01000} &
-\multicolumn{1}{c|}{aq} &
-\multicolumn{1}{c|}{rl} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{011} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0101111} & AMOOR.D rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{10000} &
-\multicolumn{1}{c|}{aq} &
-\multicolumn{1}{c|}{rl} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{011} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0101111} & AMOMIN.D rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{10100} &
-\multicolumn{1}{c|}{aq} &
-\multicolumn{1}{c|}{rl} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{011} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0101111} & AMOMAX.D rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{11000} &
-\multicolumn{1}{c|}{aq} &
-\multicolumn{1}{c|}{rl} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{011} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0101111} & AMOMINU.D rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{11100} &
-\multicolumn{1}{c|}{aq} &
-\multicolumn{1}{c|}{rl} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{011} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0101111} & AMOMAXU.D rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{10}{c}{} & \\
-&
-\multicolumn{10}{c}{\bf RV32F Standard Extension} & \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{imm[11:0]} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0000111} & FLW rd,rs1,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{imm[11:5]} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{imm[4:0]} &
-\multicolumn{1}{c|}{0100111} & FSW rs1,rs2,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{rs3} &
-\multicolumn{2}{c|}{00} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1000011} & FMADD.S rd,rs1,rs2,rs3 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{rs3} &
-\multicolumn{2}{c|}{00} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1000111} & FMSUB.S rd,rs1,rs2,rs3 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{rs3} &
-\multicolumn{2}{c|}{00} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1001011} & FNMSUB.S rd,rs1,rs2,rs3 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{rs3} &
-\multicolumn{2}{c|}{00} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1001111} & FNMADD.S rd,rs1,rs2,rs3 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000000} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FADD.S rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000100} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FSUB.S rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0001000} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FMUL.S rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0001100} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FDIV.S rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0101100} &
-\multicolumn{2}{c|}{00000} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FSQRT.S rd,rs1 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0010000} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{000} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FSGNJ.S rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0010000} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{001} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FSGNJN.S rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0010000} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FSGNJX.S rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0010100} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{000} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FMIN.S rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0010100} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{001} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FMAX.S rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{1100000} &
-\multicolumn{2}{c|}{00000} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FCVT.W.S rd,rs1 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{1100000} &
-\multicolumn{2}{c|}{00001} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FCVT.WU.S rd,rs1 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{1110000} &
-\multicolumn{2}{c|}{00000} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{000} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FMV.X.S rd,rs1 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{1010000} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FEQ.S rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{1010000} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{001} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FLT.S rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{1010000} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{000} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FLE.S rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{1110000} &
-\multicolumn{2}{c|}{00000} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{001} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FCLASS.S rd,rs1 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{1101000} &
-\multicolumn{2}{c|}{00000} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FCVT.S.W rd,rs1 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{1101000} &
-\multicolumn{2}{c|}{00001} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FCVT.S.WU rd,rs1 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{1111000} &
-\multicolumn{2}{c|}{00000} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{000} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FMV.S.X rd,rs1 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{000000000011} &
-\multicolumn{1}{c|}{00000} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1110011} & FRCSR rd \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{000000000010} &
-\multicolumn{1}{c|}{00000} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1110011} & FRRM rd \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{000000000001} &
-\multicolumn{1}{c|}{00000} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1110011} & FRFLAGS rd \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{000000000011} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{001} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1110011} & FSCSR rd,rs1 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{000000000010} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{001} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1110011} & FSRM rd,rs1 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{000000000001} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{001} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1110011} & FSFLAGS rd,rs1 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{000000000010} &
-\multicolumn{1}{c|}{00000} &
-\multicolumn{1}{c|}{101} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1110011} & FSRMI rd,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{000000000001} &
-\multicolumn{1}{c|}{00000} &
-\multicolumn{1}{c|}{101} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1110011} & FSFLAGSI rd,imm \\
-\cline{2-11}
-  
-
-\end{tabular}
-\end{center}
-\end{small}
-
-\label{instr-table}
-\end{table}
-  
-
-\newpage
-
-\begin{table}[p]
-\begin{small}
-\begin{center}
-\begin{tabular}{p{0in}p{0.4in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.4in}p{0.6in}p{0.4in}p{0.6in}p{0.7in}l}
-& & & & & & & & & & \\
-                      &
-\multicolumn{1}{l}{\instbit{31}} &
-\multicolumn{1}{r}{\instbit{27}} &
-\instbit{26} &
-\instbit{25} &
-\multicolumn{1}{l}{\instbit{24}} &
-\multicolumn{1}{r}{\instbit{20}} &
-\instbitrange{19}{15} &
-\instbitrange{14}{12} &
-\instbitrange{11}{7} &
-\instbitrange{6}{0} \\
-\cline{2-11}
-
-
-&
-\multicolumn{4}{|c|}{funct7} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{funct3} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{opcode} & R-type \\
-\cline{2-11}
-
-
-&
-\multicolumn{2}{|c|}{rs3} &
-\multicolumn{2}{c|}{funct2} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{funct3} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{opcode} & R4-type \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{imm[11:0]} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{funct3} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{opcode} & I-type \\
-\cline{2-11}
-
-
-&
-\multicolumn{4}{|c|}{imm[11:5]} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{funct3} &
-\multicolumn{1}{c|}{imm[4:0]} &
-\multicolumn{1}{c|}{opcode} & S-type \\
-\cline{2-11}
-
-
-&
-\multicolumn{10}{c}{} & \\
-&
-\multicolumn{10}{c}{\bf RV64F Standard Extension (in addition to RV32F)} & \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{1100000} &
-\multicolumn{2}{c|}{00010} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FCVT.L.S rd,rs1 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{1100000} &
-\multicolumn{2}{c|}{00011} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FCVT.LU.S rd,rs1 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{1101000} &
-\multicolumn{2}{c|}{00010} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FCVT.S.L rd,rs1 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{1101000} &
-\multicolumn{2}{c|}{00011} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FCVT.S.LU rd,rs1 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{10}{c}{} & \\
-&
-\multicolumn{10}{c}{\bf RV32D Standard Extension} & \\
-\cline{2-11}
-  
-
-&
-\multicolumn{6}{|c|}{imm[11:0]} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{011} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{0000111} & FLD rd,rs1,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{imm[11:5]} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{011} &
-\multicolumn{1}{c|}{imm[4:0]} &
-\multicolumn{1}{c|}{0100111} & FSD rs1,rs2,imm \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{rs3} &
-\multicolumn{2}{c|}{01} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1000011} & FMADD.D rd,rs1,rs2,rs3 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{rs3} &
-\multicolumn{2}{c|}{01} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1000111} & FMSUB.D rd,rs1,rs2,rs3 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{rs3} &
-\multicolumn{2}{c|}{01} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1001011} & FNMSUB.D rd,rs1,rs2,rs3 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{2}{|c|}{rs3} &
-\multicolumn{2}{c|}{01} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1001111} & FNMADD.D rd,rs1,rs2,rs3 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000001} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FADD.D rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0000101} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FSUB.D rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0001001} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FMUL.D rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0001101} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FDIV.D rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0101101} &
-\multicolumn{2}{c|}{00000} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FSQRT.D rd,rs1 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0010001} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{000} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FSGNJ.D rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0010001} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{001} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FSGNJN.D rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0010001} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FSGNJX.D rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0010101} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{000} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FMIN.D rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0010101} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{001} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FMAX.D rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0100000} &
-\multicolumn{2}{c|}{00001} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FCVT.S.D rd,rs1 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{0100001} &
-\multicolumn{2}{c|}{00000} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FCVT.D.S rd,rs1 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{1010001} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{010} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FEQ.D rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{1010001} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{001} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FLT.D rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{1010001} &
-\multicolumn{2}{c|}{rs2} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{000} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FLE.D rd,rs1,rs2 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{1110001} &
-\multicolumn{2}{c|}{00000} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{001} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FCLASS.D rd,rs1 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{1100001} &
-\multicolumn{2}{c|}{00000} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FCVT.W.D rd,rs1 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{1100001} &
-\multicolumn{2}{c|}{00001} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FCVT.WU.D rd,rs1 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{1101001} &
-\multicolumn{2}{c|}{00000} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FCVT.D.W rd,rs1 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{1101001} &
-\multicolumn{2}{c|}{00001} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FCVT.D.WU rd,rs1 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{10}{c}{} & \\
-&
-\multicolumn{10}{c}{\bf RV64D Standard Extension (in addition to RV32D)} & \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{1100001} &
-\multicolumn{2}{c|}{00010} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FCVT.L.D rd,rs1 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{1100001} &
-\multicolumn{2}{c|}{00011} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FCVT.LU.D rd,rs1 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{1110001} &
-\multicolumn{2}{c|}{00000} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{000} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FMV.X.D rd,rs1 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{1101001} &
-\multicolumn{2}{c|}{00010} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FCVT.D.L rd,rs1 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{1101001} &
-\multicolumn{2}{c|}{00011} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{rm} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FCVT.D.LU rd,rs1 \\
-\cline{2-11}
-  
-
-&
-\multicolumn{4}{|c|}{1111001} &
-\multicolumn{2}{c|}{00000} &
-\multicolumn{1}{c|}{rs1} &
-\multicolumn{1}{c|}{000} &
-\multicolumn{1}{c|}{rd} &
-\multicolumn{1}{c|}{1010011} & FMV.D.X rd,rs1 \\
-\cline{2-11}
-  
-
-\end{tabular}
-\end{center}
-\end{small}
-\caption{Instruction listing for RISC-V}
-\label{instr-table}
-\end{table}
-