From 62e3af5e10d327698986e2682788b70687a79521 Mon Sep 17 00:00:00 2001 From: Jason Gross Date: Mon, 14 Aug 2017 12:31:15 -0400 Subject: Fixup header and footer --- etc/compile-by-zinc/femulScheduled.log | 5 ++--- etc/compile-by-zinc/heuristic-search.py | 20 +++++++++++--------- 2 files changed, 13 insertions(+), 12 deletions(-) (limited to 'etc/compile-by-zinc') diff --git a/etc/compile-by-zinc/femulScheduled.log b/etc/compile-by-zinc/femulScheduled.log index 40559671b..70e059c1d 100644 --- a/etc/compile-by-zinc/femulScheduled.log +++ b/etc/compile-by-zinc/femulScheduled.log @@ -1,4 +1,4 @@ -INPUT: (x10, x11, x9, x7, x5, x18, x19, x17, x15, x13) +λ '(x10, x11, x9, x7, x5, (x18, x19, x17, x15, x13))%core, uint128_t x20 = (uint128_t) x5 * x13; // MULX r64,r64,r64, start: 0, end: 4 uint128_t x21 = (uint128_t) x5 * x15; // MULX r64,r64,r64, start: 1, end: 5 uint128_t x24 = (uint128_t) x5 * x17; // MULX r64,r64,r64, start: 2, end: 6 @@ -70,5 +70,4 @@ uint64_t x87 = x85 + x73; // ADD, start: 62, end: 63 uint64_t x88 = x87 >> 0x33; // SHR r,i, start: 63, end: 64 uint64_t x89 = x87 & 0x7ffffffffffff; // AND, start: 63, end: 64 uint64_t x90 = x88 + x76; // ADD, start: 64, end: 65 -Return (x82, x79, x90, x89, x86) -// end: 65 +return (x82, x79, x90, x89, x86)) diff --git a/etc/compile-by-zinc/heuristic-search.py b/etc/compile-by-zinc/heuristic-search.py index ba979f5dd..12223eadb 100755 --- a/etc/compile-by-zinc/heuristic-search.py +++ b/etc/compile-by-zinc/heuristic-search.py @@ -131,10 +131,12 @@ def parse_lines(lines): ret['vars'] = lines[0][len(LAMBDA + ' '):-1] assert lines[-1][-1] == ')' ret['return'] = lines[-1][:-1].replace('return ', '').replace('Return ', '') + ret['header'] = orig_lines[0] + ret['footer'] = orig_lines[-1] ret['lines'] = [] var_types = dict((var, 'uint64_t') for var in get_input_var_names(ret)) for line, orig_line in zip(lines, orig_lines)[1:-1]: - datatype, varname, arg1, op, arg2 = re.findall('^(u?int[0-9]*_t) ([^ ]*) = ([^ ]*) ([^ ]*) ([^ ]*);$', line)[0] + datatype, varname, arg1, op, arg2 = re.findall('^(u?int[0-9]*_t) ([^ ]*) = ([^ ]*) ([^ ]*) ([^ ]*);(?: // .*)?$', line)[0] var_types[varname] = datatype cur_line = {'type':datatype, 'out':varname, 'op':op, 'args':(arg1, arg2), 'source':orig_line} possible_cores = possible_cores_for_line(cur_line, var_types) @@ -380,21 +382,21 @@ def schedule(data, basepoint, do_print): schedule_with_cycle_info = add_cycle_info(schedule) for var, cycles, core in schedule_with_cycle_info: if var in lines.keys(): - do_print('%s // %s, start: %s, end: %s' % (lines[var]['source'], core['instruction'], basepoint + cycles['start'], basepoint + cycles['finish'])) + do_print(lines[var]['source'], ' // %s, start: %s, end: %s' % (core['instruction'], basepoint + cycles['start'], basepoint + cycles['finish'])) else: - do_print('%s = %s; // %s, start: %s, end: %s' % (var, core['instruction'], basepoint + cycles['start'], basepoint + cycles['finish'])) + do_print('%s = %s;' % (var, var), ' // %s, start: %s, end: %s' % (core['instruction'], basepoint + cycles['start'], basepoint + cycles['finish'])) return basepoint + cost data_list = parse_lines(get_lines('femulDisplay.log')) basepoint = 0 for i, data in enumerate(data_list): - with open('femulScheduled.log', 'w') as f: - def do_print(v): - print(v) - f.write(v + '\n') - f.write('INPUT: (%s)\n' % ', '.join(get_input_var_names(data))) + with codecs.open('femulScheduled.log', 'w', encoding='utf8') as f: + def do_print(v, comment): + print(v + comment) + f.write(v + comment + '\n') + f.write(data['header'] + '\n') basepoint = schedule(data, basepoint, do_print) - f.write('Return (%s)\n// end: %d\n' % (', '.join(get_output_var_names(data)), basepoint)) + f.write(data['footer'] + '\n') print(basepoint) sys.exit(0) -- cgit v1.2.3