From 0fc8954282140d00b47ee1d298c4d4bce35aa724 Mon Sep 17 00:00:00 2001 From: Gael Guennebaud Date: Tue, 27 Oct 2015 10:38:49 +0100 Subject: Improve readibility of EIGEN_DEBUG_ASSIGN mode. --- test/vectorization_logic.cpp | 32 +++----------------------------- 1 file changed, 3 insertions(+), 29 deletions(-) (limited to 'test/vectorization_logic.cpp') diff --git a/test/vectorization_logic.cpp b/test/vectorization_logic.cpp index 6ff38ed11..da60a2f3a 100644 --- a/test/vectorization_logic.cpp +++ b/test/vectorization_logic.cpp @@ -11,35 +11,9 @@ #include "main.h" #include -std::string demangle_traversal(int t) -{ - if(t==DefaultTraversal) return "DefaultTraversal"; - if(t==LinearTraversal) return "LinearTraversal"; - if(t==InnerVectorizedTraversal) return "InnerVectorizedTraversal"; - if(t==LinearVectorizedTraversal) return "LinearVectorizedTraversal"; - if(t==SliceVectorizedTraversal) return "SliceVectorizedTraversal"; - return "?"; -} -std::string demangle_unrolling(int t) -{ - if(t==NoUnrolling) return "NoUnrolling"; - if(t==InnerUnrolling) return "InnerUnrolling"; - if(t==CompleteUnrolling) return "CompleteUnrolling"; - return "?"; -} -std::string demangle_flags(int f) -{ - std::string res; - if(f&RowMajorBit) res += " | RowMajor"; - if(f&PacketAccessBit) res += " | Packet"; - if(f&LinearAccessBit) res += " | Linear"; - if(f&LvalueBit) res += " | Lvalue"; - if(f&DirectAccessBit) res += " | Direct"; - if(f&NestByRefBit) res += " | NestByRef"; - if(f&NoPreferredStorageOrderBit) res += " | NoPreferredStorageOrderBit"; - - return res; -} +using internal::demangle_flags; +using internal::demangle_traversal; +using internal::demangle_unrolling; template bool test_assign(const Dst&, const Src&, int traversal, int unrolling) -- cgit v1.2.3