From 615fb53c13f2407a0b6b470bbdf8e468fc4a1d78 Mon Sep 17 00:00:00 2001 From: xleroy Date: Fri, 5 Jun 2009 13:39:59 +0000 Subject: Adapted to work with Coq 8.2-1 git-svn-id: https://yquem.inria.fr/compcert/svn/compcert/trunk@1076 fca1b0fc-160b-0410-b1d3-a4f43f01ea2e --- lib/Integers.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'lib/Integers.v') diff --git a/lib/Integers.v b/lib/Integers.v index ceda851..1eb59c5 100644 --- a/lib/Integers.v +++ b/lib/Integers.v @@ -23,7 +23,7 @@ Definition half_modulus : Z := modulus / 2. (** * Comparisons *) -Inductive comparison : Set := +Inductive comparison : Type := | Ceq : comparison (**r same *) | Cne : comparison (**r different *) | Clt : comparison (**r less than *) @@ -57,7 +57,7 @@ Definition swap_comparison (c: comparison): comparison := integer (type [Z]) plus a proof that it is in the range 0 (included) to [modulus] (excluded. *) -Record int: Set := mkint { intval: Z; intrange: 0 <= intval < modulus }. +Record int: Type := mkint { intval: Z; intrange: 0 <= intval < modulus }. Module Int. @@ -289,7 +289,7 @@ Definition is_power2 (x: int) : option int := >> *) -Inductive rlw_state: Set := +Inductive rlw_state: Type := | RLW_S0 : rlw_state | RLW_S1 : rlw_state | RLW_S2 : rlw_state -- cgit v1.2.3