From 6c26ec72a5b299a5ceb3e4ca7ed0712d312da548 Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Fri, 2 Jan 2015 20:59:23 +0100 Subject: Pica/CommandProcessor: Properly implement shader load destination offset registers. --- src/video_core/pica.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'src/video_core/pica.h') diff --git a/src/video_core/pica.h b/src/video_core/pica.h index 9c1a12dc..cf9dc485 100644 --- a/src/video_core/pica.h +++ b/src/video_core/pica.h @@ -678,7 +678,9 @@ struct Regs { INSERT_PADDING_WORDS(0x2); struct { - u32 begin_load; + // Offset of the next instruction to write code to. + // Incremented with each instruction write. + u32 offset; // Writing to these registers sets the "current" word in the shader program. // TODO: It's not clear how the hardware stores what the "current" word is. @@ -690,7 +692,9 @@ struct Regs { // This register group is used to load an internal table of swizzling patterns, // which are indexed by each shader instruction to specify vector component swizzling. struct { - u32 begin_load; + // Offset of the next swizzle pattern to write code to. + // Incremented with each instruction write. + u32 offset; // Writing to these registers sets the "current" swizzle pattern in the table. // TODO: It's not clear how the hardware stores what the "current" swizzle pattern is. -- cgit v1.2.3