From 02c9fe202c4027d7e4a6287137f4b254b8830494 Mon Sep 17 00:00:00 2001
From: bunnei <bunneidev@gmail.com>
Date: Sun, 24 May 2015 00:55:35 -0400
Subject: Pica: Implement command buffer execution registers.

---
 src/video_core/pica.h | 50 ++++++++++++++++++++++++++++++++++++++------------
 1 file changed, 38 insertions(+), 12 deletions(-)

(limited to 'src/video_core/pica.h')

diff --git a/src/video_core/pica.h b/src/video_core/pica.h
index 6ebeb08f..fbc95a4b 100644
--- a/src/video_core/pica.h
+++ b/src/video_core/pica.h
@@ -708,7 +708,33 @@ struct Regs {
         u32 set_value[3];
     } vs_default_attributes_setup;
 
-    INSERT_PADDING_WORDS(0x28);
+    INSERT_PADDING_WORDS(0x2);
+
+    struct {
+        // There are two channels that can be used to configure the next command buffer, which
+        // can be then executed by writing to the "trigger" registers. There are two reasons why a
+        // game might use this feature:
+        //  1) With this, an arbitrary number of additional command buffers may be executed in
+        //     sequence without requiring any intervention of the CPU after the initial one is
+        //     kicked off.
+        //  2) Games can configure these registers to provide a command list subroutine mechanism.
+
+        BitField< 0, 20, u32> size[2]; ///< Size (in bytes / 8) of each channel's command buffer
+        BitField< 0, 28, u32> addr[2]; ///< Physical address / 8 of each channel's command buffer
+        u32 trigger[2]; ///< Triggers execution of the channel's command buffer when written to
+
+        unsigned GetSize(unsigned index) const {
+            ASSERT(index < 2);
+            return 8 * size[index];
+        }
+
+        PAddr GetPhysicalAddress(unsigned index) const {
+            ASSERT(index < 2);
+            return (PAddr)(8 * addr[index]);
+        }
+    } command_buffer;
+
+    INSERT_PADDING_WORDS(0x20);
 
     enum class TriangleTopology : u32 {
         List        = 0,
@@ -861,6 +887,7 @@ struct Regs {
         ADD_FIELD(trigger_draw);
         ADD_FIELD(trigger_draw_indexed);
         ADD_FIELD(vs_default_attributes_setup);
+        ADD_FIELD(command_buffer);
         ADD_FIELD(triangle_topology);
         ADD_FIELD(vs_bool_uniforms);
         ADD_FIELD(vs_int_uniforms);
@@ -938,6 +965,7 @@ ASSERT_REG_POSITION(num_vertices, 0x228);
 ASSERT_REG_POSITION(trigger_draw, 0x22e);
 ASSERT_REG_POSITION(trigger_draw_indexed, 0x22f);
 ASSERT_REG_POSITION(vs_default_attributes_setup, 0x232);
+ASSERT_REG_POSITION(command_buffer, 0x238);
 ASSERT_REG_POSITION(triangle_topology, 0x25e);
 ASSERT_REG_POSITION(vs_bool_uniforms, 0x2b0);
 ASSERT_REG_POSITION(vs_int_uniforms, 0x2b1);
@@ -1053,21 +1081,12 @@ private:
     float value;
 };
 
-union CommandHeader {
-    CommandHeader(u32 h) : hex(h) {}
-
-    u32 hex;
-
-    BitField< 0, 16, u32> cmd_id;
-    BitField<16,  4, u32> parameter_mask;
-    BitField<20, 11, u32> extra_data_length;
-    BitField<31,  1, u32> group_commands;
-};
-
 /// Struct used to describe current Pica state
 struct State {
+    /// Pica registers
     Regs regs;
 
+    /// Vertex shader memory
     struct {
         struct {
             Math::Vec4<float24> f[96];
@@ -1080,6 +1099,13 @@ struct State {
         std::array<u32, 1024> program_code;
         std::array<u32, 1024> swizzle_data;
     } vs;
+
+    /// Current Pica command list
+    struct {
+        const u32* head_ptr;
+        const u32* current_ptr;
+        u32 length;
+    } cmd_list;
 };
 
 /// Initialize Pica state
-- 
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