From 85b1dddda12ebe339cfc462845f899546ffabe41 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sun, 31 May 2015 05:32:46 -0400 Subject: arm_dyncom_thumb: Implement CPS and SETEND --- src/core/arm/dyncom/arm_dyncom_thumb.cpp | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'src/core/arm') diff --git a/src/core/arm/dyncom/arm_dyncom_thumb.cpp b/src/core/arm/dyncom/arm_dyncom_thumb.cpp index 270d966b..897bb046 100644 --- a/src/core/arm/dyncom/arm_dyncom_thumb.cpp +++ b/src/core/arm/dyncom/arm_dyncom_thumb.cpp @@ -287,6 +287,19 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) { *ainstr = subset[BITS(tinstr, 6, 7)] // base | (BITS(tinstr, 0, 2) << 12) // Rd | BITS(tinstr, 3, 5); // Rm + } else if ((tinstr & 0x0F00) == 0x600) { + if (BIT(tinstr, 5) == 0) { + // SETEND + *ainstr = 0xF1010000 // base + | (BIT(tinstr, 3) << 9); // endian specifier + } else { + // CPS + *ainstr = 0xF1080000 // base + | (BIT(tinstr, 0) << 6) // fiq bit + | (BIT(tinstr, 1) << 7) // irq bit + | (BIT(tinstr, 2) << 8) // abort bit + | (BIT(tinstr, 4) << 18); // enable bit + } } else if ((tinstr & 0x0F00) == 0x0a00) { static const ARMword subset[3] = { 0xE6BF0F30, // REV -- cgit v1.2.3