From 7caef19c89662b5c80c4f1ea6d8862dcf7760b17 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sun, 31 May 2015 04:42:39 -0400 Subject: arm_dyncom_thumb: Implement SXTH, SXTB, UXTH, and UXTB. --- src/core/arm/dyncom/arm_dyncom_thumb.cpp | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'src/core/arm') diff --git a/src/core/arm/dyncom/arm_dyncom_thumb.cpp b/src/core/arm/dyncom/arm_dyncom_thumb.cpp index 78552293..270d966b 100644 --- a/src/core/arm/dyncom/arm_dyncom_thumb.cpp +++ b/src/core/arm/dyncom/arm_dyncom_thumb.cpp @@ -276,6 +276,17 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) { |(tinstr & 0x007F); // off7 } else if ((tinstr & 0x0F00) == 0x0e00) { *ainstr = 0xEF000000 | 0x180000; // base | BKPT mask + } else if ((tinstr & 0x0F00) == 0x0200) { + static const ARMword subset[4] = { + 0xE6BF0070, // SXTH + 0xE6AF0070, // SXTB + 0xE6FF0070, // UXTH + 0xE6EF0070, // UXTB + }; + + *ainstr = subset[BITS(tinstr, 6, 7)] // base + | (BITS(tinstr, 0, 2) << 12) // Rd + | BITS(tinstr, 3, 5); // Rm } else if ((tinstr & 0x0F00) == 0x0a00) { static const ARMword subset[3] = { 0xE6BF0F30, // REV -- cgit v1.2.3