From dfb424b6d1238fed41cf1305ae1b330d5c4c5a0d Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 25 Jul 2015 21:10:41 -0400 Subject: dyncom: Rename armdefs.h to armstate.h --- src/core/arm/skyeye_common/armstate.h | 279 ++++++++++++++++++++++++++++++++++ 1 file changed, 279 insertions(+) create mode 100644 src/core/arm/skyeye_common/armstate.h (limited to 'src/core/arm/skyeye_common/armstate.h') diff --git a/src/core/arm/skyeye_common/armstate.h b/src/core/arm/skyeye_common/armstate.h new file mode 100644 index 00000000..f1af0221 --- /dev/null +++ b/src/core/arm/skyeye_common/armstate.h @@ -0,0 +1,279 @@ +/* armdefs.h -- ARMulator common definitions: ARM6 Instruction Emulator. + Copyright (C) 1994 Advanced RISC Machines Ltd. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#pragma once + +#include + +#include "common/common_types.h" +#include "core/arm/skyeye_common/arm_regformat.h" + +// Signal levels +enum { + LOW = 0, + HIGH = 1, + LOWHIGH = 1, + HIGHLOW = 2 +}; + +// Cache types +enum { + NONCACHE = 0, + DATACACHE = 1, + INSTCACHE = 2, +}; + +// Abort models +enum { + ABORT_BASE_RESTORED = 0, + ABORT_EARLY = 1, + ABORT_BASE_UPDATED = 2 +}; + +#define VFP_REG_NUM 64 +struct ARMul_State +{ + u32 Emulate; // To start and stop emulation + + // Order of the following register should not be modified + u32 Reg[16]; // The current register file + u32 Cpsr; // The current PSR + u32 Spsr_copy; + u32 phys_pc; + u32 Reg_usr[2]; + u32 Reg_svc[2]; // R13_SVC R14_SVC + u32 Reg_abort[2]; // R13_ABORT R14_ABORT + u32 Reg_undef[2]; // R13 UNDEF R14 UNDEF + u32 Reg_irq[2]; // R13_IRQ R14_IRQ + u32 Reg_firq[7]; // R8---R14 FIRQ + u32 Spsr[7]; // The exception psr's + u32 Mode; // The current mode + u32 Bank; // The current register bank + u32 exclusive_tag; // The address for which the local monitor is in exclusive access mode + u32 exclusive_state; + u32 exclusive_result; + u32 CP15[CP15_REGISTER_COUNT]; + + // FPSID, FPSCR, and FPEXC + u32 VFP[VFP_SYSTEM_REGISTER_COUNT]; + // VFPv2 and VFPv3-D16 has 16 doubleword registers (D0-D16 or S0-S31). + // VFPv3-D32/ASIMD may have up to 32 doubleword registers (D0-D31), + // and only 32 singleword registers are accessible (S0-S31). + u32 ExtReg[VFP_REG_NUM]; + /* ---- End of the ordered registers ---- */ + + u32 NFlag, ZFlag, CFlag, VFlag, IFFlags; // Dummy flags for speed + unsigned int shifter_carry_out; + + // Add armv6 flags dyf:2010-08-09 + u32 GEFlag, EFlag, AFlag, QFlag; + + u32 TFlag; // Thumb state + + unsigned long long NumInstrs; // The number of instructions executed + unsigned NumInstrsToExecute; + + unsigned NresetSig; // Reset the processor + unsigned NfiqSig; + unsigned NirqSig; + + unsigned abortSig; + unsigned NtransSig; + unsigned bigendSig; + unsigned syscallSig; + +/* 2004-05-09 chy +---------------------------------------------------------- +read ARM Architecture Reference Manual +2.6.5 Data Abort +There are three Abort Model in ARM arch. + +Early Abort Model: used in some ARMv3 and earlier implementations. In this +model, base register wirteback occurred for LDC,LDM,STC,STM instructions, and +the base register was unchanged for all other instructions. (oldest) + +Base Restored Abort Model: If a Data Abort occurs in an instruction which +specifies base register writeback, the value in the base register is +unchanged. (strongarm, xscale) + +Base Updated Abort Model: If a Data Abort occurs in an instruction which +specifies base register writeback, the base register writeback still occurs. +(arm720T) + +read PART B +chap2 The System Control Coprocessor CP15 +2.4 Register1:control register +L(bit 6): in some ARMv3 and earlier implementations, the abort model of the +processor could be configured: +0=early Abort Model Selected(now obsolete) +1=Late Abort Model selceted(same as Base Updated Abort Model) + +on later processors, this bit reads as 1 and ignores writes. +------------------------------------------------------------- +So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model) + if lateabtSig=0, then it means Base Restored Abort Model +*/ + unsigned lateabtSig; + + // For differentiating ARM core emulaiton. + bool is_v4; // Are we emulating a v4 architecture (or higher)? + bool is_v5; // Are we emulating a v5 architecture? + bool is_v5e; // Are we emulating a v5e architecture? + bool is_v6; // Are we emulating a v6 architecture? + bool is_v7; // Are we emulating a v7 architecture? + + // ARM_ARM A2-18 + // 0 Base Restored Abort Model, 1 the Early Abort Model, 2 Base Updated Abort Model + int abort_model; + + // TODO(bunnei): Move this cache to a better place - it should be per codeset (likely per + // process for our purposes), not per ARMul_State (which tracks CPU core state). + std::unordered_map instruction_cache; +}; + +/***************************************************************************\ +* Types of ARM we know about * +\***************************************************************************/ + +enum { + ARM_v4_Prop = 0x01, + ARM_v5_Prop = 0x02, + ARM_v5e_Prop = 0x04, + ARM_v6_Prop = 0x08, + ARM_v7_Prop = 0x10, +}; + +/***************************************************************************\ +* The hardware vector addresses * +\***************************************************************************/ + +enum { + ARMResetV = 0, + ARMUndefinedInstrV = 4, + ARMSWIV = 8, + ARMPrefetchAbortV = 12, + ARMDataAbortV = 16, + ARMAddrExceptnV = 20, + ARMIRQV = 24, + ARMFIQV = 28, + ARMErrorV = 32, // This is an offset, not an address! + + ARMul_ResetV = ARMResetV, + ARMul_UndefinedInstrV = ARMUndefinedInstrV, + ARMul_SWIV = ARMSWIV, + ARMul_PrefetchAbortV = ARMPrefetchAbortV, + ARMul_DataAbortV = ARMDataAbortV, + ARMul_AddrExceptnV = ARMAddrExceptnV, + ARMul_IRQV = ARMIRQV, + ARMul_FIQV = ARMFIQV +}; + +/***************************************************************************\ +* Mode and Bank Constants * +\***************************************************************************/ + +enum PrivilegeMode { + USER32MODE = 16, + FIQ32MODE = 17, + IRQ32MODE = 18, + SVC32MODE = 19, + ABORT32MODE = 23, + UNDEF32MODE = 27, + SYSTEM32MODE = 31 +}; + +enum { + USERBANK = 0, + FIQBANK = 1, + IRQBANK = 2, + SVCBANK = 3, + ABORTBANK = 4, + UNDEFBANK = 5, + DUMMYBANK = 6, + SYSTEMBANK = 7 +}; + +/***************************************************************************\ +* Definitions of things in the emulator * +\***************************************************************************/ +void ARMul_Reset(ARMul_State* state); +ARMul_State* ARMul_NewState(ARMul_State* state); + +/***************************************************************************\ +* Definitions of things in the co-processor interface * +\***************************************************************************/ + +enum { + ARMul_FIRST = 0, + ARMul_TRANSFER = 1, + ARMul_BUSY = 2, + ARMul_DATA = 3, + ARMul_INTERRUPT = 4, + ARMul_DONE = 0, + ARMul_CANT = 1, + ARMul_INC = 3 +}; + +/***************************************************************************\ +* Definitions of things in the host environment * +\***************************************************************************/ + +enum ConditionCode { + EQ = 0, + NE = 1, + CS = 2, + CC = 3, + MI = 4, + PL = 5, + VS = 6, + VC = 7, + HI = 8, + LS = 9, + GE = 10, + LT = 11, + GT = 12, + LE = 13, + AL = 14, + NV = 15, +}; + +// Flags for use with the APSR. +enum : u32 { + NBIT = (1U << 31U), + ZBIT = (1 << 30), + CBIT = (1 << 29), + VBIT = (1 << 28), + QBIT = (1 << 27), + JBIT = (1 << 24), + EBIT = (1 << 9), + ABIT = (1 << 8), + IBIT = (1 << 7), + FBIT = (1 << 6), + TBIT = (1 << 5), + + // Masks for groups of bits in the APSR. + MODEBITS = 0x1F, + INTBITS = 0x1C0, +}; + +// Values for Emulate. +enum { + STOP = 0, // Stop + CHANGEMODE = 1, // Change mode + ONCE = 2, // Execute just one iteration + RUN = 3 // Continuous execution +}; -- cgit v1.2.3 From 3257d797e1f981be0fea87942443ff25fe841e03 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 25 Jul 2015 21:31:47 -0400 Subject: dyncom: Remove unnecessary abort-related cruft Both the MPCore and the ARM9 have the same data abort model (base restored), so differentiating isn't necessary. --- src/core/arm/dyncom/arm_dyncom.cpp | 3 --- src/core/arm/skyeye_common/armstate.h | 46 +---------------------------------- 2 files changed, 1 insertion(+), 48 deletions(-) (limited to 'src/core/arm/skyeye_common/armstate.h') diff --git a/src/core/arm/dyncom/arm_dyncom.cpp b/src/core/arm/dyncom/arm_dyncom.cpp index 3f93b439..8d4a7dd9 100644 --- a/src/core/arm/dyncom/arm_dyncom.cpp +++ b/src/core/arm/dyncom/arm_dyncom.cpp @@ -23,10 +23,7 @@ ARM_DynCom::ARM_DynCom(PrivilegeMode initial_mode) { ARMul_NewState(state.get()); ARMul_SelectProcessor(state.get(), ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop); - state->abort_model = ABORT_BASE_RESTORED; - state->bigendSig = LOW; - state->lateabtSig = LOW; state->NirqSig = HIGH; // Reset the core to initial state diff --git a/src/core/arm/skyeye_common/armstate.h b/src/core/arm/skyeye_common/armstate.h index f1af0221..0a165bcf 100644 --- a/src/core/arm/skyeye_common/armstate.h +++ b/src/core/arm/skyeye_common/armstate.h @@ -37,13 +37,6 @@ enum { INSTCACHE = 2, }; -// Abort models -enum { - ABORT_BASE_RESTORED = 0, - ABORT_EARLY = 1, - ABORT_BASE_UPDATED = 2 -}; - #define VFP_REG_NUM 64 struct ARMul_State { @@ -96,50 +89,13 @@ struct ARMul_State unsigned bigendSig; unsigned syscallSig; -/* 2004-05-09 chy ----------------------------------------------------------- -read ARM Architecture Reference Manual -2.6.5 Data Abort -There are three Abort Model in ARM arch. - -Early Abort Model: used in some ARMv3 and earlier implementations. In this -model, base register wirteback occurred for LDC,LDM,STC,STM instructions, and -the base register was unchanged for all other instructions. (oldest) - -Base Restored Abort Model: If a Data Abort occurs in an instruction which -specifies base register writeback, the value in the base register is -unchanged. (strongarm, xscale) - -Base Updated Abort Model: If a Data Abort occurs in an instruction which -specifies base register writeback, the base register writeback still occurs. -(arm720T) - -read PART B -chap2 The System Control Coprocessor CP15 -2.4 Register1:control register -L(bit 6): in some ARMv3 and earlier implementations, the abort model of the -processor could be configured: -0=early Abort Model Selected(now obsolete) -1=Late Abort Model selceted(same as Base Updated Abort Model) - -on later processors, this bit reads as 1 and ignores writes. -------------------------------------------------------------- -So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model) - if lateabtSig=0, then it means Base Restored Abort Model -*/ - unsigned lateabtSig; - - // For differentiating ARM core emulaiton. + // For differentiating ARM core emulation. bool is_v4; // Are we emulating a v4 architecture (or higher)? bool is_v5; // Are we emulating a v5 architecture? bool is_v5e; // Are we emulating a v5e architecture? bool is_v6; // Are we emulating a v6 architecture? bool is_v7; // Are we emulating a v7 architecture? - // ARM_ARM A2-18 - // 0 Base Restored Abort Model, 1 the Early Abort Model, 2 Base Updated Abort Model - int abort_model; - // TODO(bunnei): Move this cache to a better place - it should be per codeset (likely per // process for our purposes), not per ARMul_State (which tracks CPU core state). std::unordered_map instruction_cache; -- cgit v1.2.3 From 03213f893e7f2cbd692144334ac72d9138fd5e70 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 25 Jul 2015 21:55:52 -0400 Subject: dyncom: Remove unnecessary initialization code. Targeting ARM version variants was only a thing on armemu. The reset routine also does basically the same thing as NewState. --- src/core/arm/dyncom/arm_dyncom.cpp | 7 ------- src/core/arm/skyeye_common/arminit.cpp | 32 ++------------------------------ src/core/arm/skyeye_common/armstate.h | 20 -------------------- src/core/arm/skyeye_common/armsupp.h | 2 -- 4 files changed, 2 insertions(+), 59 deletions(-) (limited to 'src/core/arm/skyeye_common/armstate.h') diff --git a/src/core/arm/dyncom/arm_dyncom.cpp b/src/core/arm/dyncom/arm_dyncom.cpp index 8d4a7dd9..a51a3acf 100644 --- a/src/core/arm/dyncom/arm_dyncom.cpp +++ b/src/core/arm/dyncom/arm_dyncom.cpp @@ -20,15 +20,8 @@ ARM_DynCom::ARM_DynCom(PrivilegeMode initial_mode) { state = Common::make_unique(); - ARMul_NewState(state.get()); - ARMul_SelectProcessor(state.get(), ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop); - - state->bigendSig = LOW; - state->NirqSig = HIGH; - // Reset the core to initial state ARMul_Reset(state.get()); - state->Emulate = RUN; // Switch to the desired privilege mode. switch_mode(state.get(), initial_mode); diff --git a/src/core/arm/skyeye_common/arminit.cpp b/src/core/arm/skyeye_common/arminit.cpp index 4e868f86..b7c508d7 100644 --- a/src/core/arm/skyeye_common/arminit.cpp +++ b/src/core/arm/skyeye_common/arminit.cpp @@ -19,33 +19,6 @@ #include "core/arm/skyeye_common/armstate.h" #include "core/arm/skyeye_common/vfp/vfp.h" -/***************************************************************************\ -* Returns a new instantiation of the ARMulator's state * -\***************************************************************************/ -ARMul_State* ARMul_NewState(ARMul_State* state) -{ - state->Emulate = RUN; - state->Mode = USER32MODE; - - state->lateabtSig = HIGH; - state->bigendSig = LOW; - - return state; -} - -/***************************************************************************\ -* Call this routine to set ARMulator to model a certain processor * -\***************************************************************************/ - -void ARMul_SelectProcessor(ARMul_State* state, unsigned properties) -{ - state->is_v4 = (properties & (ARM_v4_Prop | ARM_v5_Prop)) != 0; - state->is_v5 = (properties & ARM_v5_Prop) != 0; - state->is_v5e = (properties & ARM_v5e_Prop) != 0; - state->is_v6 = (properties & ARM_v6_Prop) != 0; - state->is_v7 = (properties & ARM_v7_Prop) != 0; -} - // Resets certain MPCore CP15 values to their ARM-defined reset values. static void ResetMPCoreCP15Registers(ARMul_State* cpu) { @@ -104,9 +77,7 @@ static void ResetMPCoreCP15Registers(ARMul_State* cpu) cpu->CP15[CP15_TLB_DEBUG_CONTROL] = 0x00000000; } -/***************************************************************************\ -* Call this routine to set up the initial machine state (or perform a RESET * -\***************************************************************************/ +// Performs a reset void ARMul_Reset(ARMul_State* state) { VFPInit(state); @@ -125,4 +96,5 @@ void ARMul_Reset(ARMul_State* state) state->abortSig = LOW; state->NumInstrs = 0; + state->Emulate = RUN; } diff --git a/src/core/arm/skyeye_common/armstate.h b/src/core/arm/skyeye_common/armstate.h index 0a165bcf..3ba0ba5c 100644 --- a/src/core/arm/skyeye_common/armstate.h +++ b/src/core/arm/skyeye_common/armstate.h @@ -89,30 +89,11 @@ struct ARMul_State unsigned bigendSig; unsigned syscallSig; - // For differentiating ARM core emulation. - bool is_v4; // Are we emulating a v4 architecture (or higher)? - bool is_v5; // Are we emulating a v5 architecture? - bool is_v5e; // Are we emulating a v5e architecture? - bool is_v6; // Are we emulating a v6 architecture? - bool is_v7; // Are we emulating a v7 architecture? - // TODO(bunnei): Move this cache to a better place - it should be per codeset (likely per // process for our purposes), not per ARMul_State (which tracks CPU core state). std::unordered_map instruction_cache; }; -/***************************************************************************\ -* Types of ARM we know about * -\***************************************************************************/ - -enum { - ARM_v4_Prop = 0x01, - ARM_v5_Prop = 0x02, - ARM_v5e_Prop = 0x04, - ARM_v6_Prop = 0x08, - ARM_v7_Prop = 0x10, -}; - /***************************************************************************\ * The hardware vector addresses * \***************************************************************************/ @@ -167,7 +148,6 @@ enum { * Definitions of things in the emulator * \***************************************************************************/ void ARMul_Reset(ARMul_State* state); -ARMul_State* ARMul_NewState(ARMul_State* state); /***************************************************************************\ * Definitions of things in the co-processor interface * diff --git a/src/core/arm/skyeye_common/armsupp.h b/src/core/arm/skyeye_common/armsupp.h index d82b2110..5cf1cd1d 100644 --- a/src/core/arm/skyeye_common/armsupp.h +++ b/src/core/arm/skyeye_common/armsupp.h @@ -17,8 +17,6 @@ struct ARMul_State; bool AddOverflow(u32, u32, u32); bool SubOverflow(u32, u32, u32); -void ARMul_SelectProcessor(ARMul_State*, unsigned); - u32 AddWithCarry(u32, u32, u32, bool*, bool*); bool ARMul_AddOverflowQ(u32, u32); -- cgit v1.2.3