From 4d8831890321c11e2e29ed9bc87c8a48841b702e Mon Sep 17 00:00:00 2001 From: bunnei Date: Sat, 12 Apr 2014 01:36:39 -0400 Subject: hacked CPU interpreter to ignore branch on SVC instruction (as we are HLEing this...) --- src/core/arm/interpreter/arminit.cpp | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'src/core/arm/interpreter/arminit.cpp') diff --git a/src/core/arm/interpreter/arminit.cpp b/src/core/arm/interpreter/arminit.cpp index cdbd02f3..a8aeecde 100644 --- a/src/core/arm/interpreter/arminit.cpp +++ b/src/core/arm/interpreter/arminit.cpp @@ -530,9 +530,13 @@ ARMul_Abort (ARMul_State * state, ARMword vector) isize); break; case ARMul_SWIV: /* Software Interrupt */ - SETABORT (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE, + // Modified SETABORT that doesn't branch to a SVC vector as we are implementing this in HLE + // Instead of doing normal routine, backup R15 by one instruction (this is what PC will get + // set to, making it the next instruction after the SVC call), and skip setting the LR. + SETABORT_SKIPBRANCH (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE, isize); - break; + state->Reg[15] -= 4; + return; case ARMul_PrefetchAbortV: /* Prefetch Abort */ state->AbortAddr = 1; SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, -- cgit v1.2.3