From 2e420aba3c007bff84988cf1c281db73c12c7f9a Mon Sep 17 00:00:00 2001 From: Lioncash Date: Wed, 29 Jul 2015 04:13:46 -0400 Subject: dyncom: Handle the case where PC is the source register for STR/VSTM/VLDM --- src/core/arm/dyncom/arm_dyncom_interpreter.cpp | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'src/core/arm/dyncom') diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp index 0c20c2bc..759ef728 100644 --- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp +++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp @@ -5997,7 +5997,12 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_cream->get_addr(cpu, inst_cream->inst, addr); - unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)]; + unsigned int reg = BITS(inst_cream->inst, 12, 15); + unsigned int value = cpu->Reg[reg]; + + if (reg == 15) + value += 2 * cpu->GetInstructionSize(); + cpu->WriteMemory32(addr, value); } cpu->Reg[15] += cpu->GetInstructionSize(); -- cgit v1.2.3