From 6c26ec72a5b299a5ceb3e4ca7ed0712d312da548 Mon Sep 17 00:00:00 2001 From: Tony Wasserka Date: Fri, 2 Jan 2015 20:59:23 +0100 Subject: Pica/CommandProcessor: Properly implement shader load destination offset registers. --- src/video_core/command_processor.cpp | 22 ++++------------------ src/video_core/pica.h | 8 ++++++-- 2 files changed, 10 insertions(+), 20 deletions(-) diff --git a/src/video_core/command_processor.cpp b/src/video_core/command_processor.cpp index b2cc0f02..586ad62b 100644 --- a/src/video_core/command_processor.cpp +++ b/src/video_core/command_processor.cpp @@ -25,10 +25,6 @@ static int float_regs_counter = 0; static u32 uniform_write_buffer[4]; -// Used for VSLoadProgramData and VSLoadSwizzleData -static u32 vs_binary_write_offset = 0; -static u32 vs_swizzle_write_offset = 0; - static inline void WritePicaReg(u32 id, u32 value, u32 mask) { if (id >= registers.NumIds()) @@ -258,11 +254,6 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) { break; } - // Seems to be used to reset the write pointer for VSLoadProgramData - case PICA_REG_INDEX(vs_program.begin_load): - vs_binary_write_offset = 0; - break; - // Load shader program code case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[0], 0x2cc): case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[1], 0x2cd): @@ -273,16 +264,11 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) { case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[6], 0x2d2): case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[7], 0x2d3): { - VertexShader::SubmitShaderMemoryChange(vs_binary_write_offset, value); - vs_binary_write_offset++; + VertexShader::SubmitShaderMemoryChange(registers.vs_program.offset, value); + registers.vs_program.offset++; break; } - // Seems to be used to reset the write pointer for VSLoadSwizzleData - case PICA_REG_INDEX(vs_swizzle_patterns.begin_load): - vs_swizzle_write_offset = 0; - break; - // Load swizzle pattern data case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[0], 0x2d6): case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[1], 0x2d7): @@ -293,8 +279,8 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) { case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[6], 0x2dc): case PICA_REG_INDEX_WORKAROUND(vs_swizzle_patterns.set_word[7], 0x2dd): { - VertexShader::SubmitSwizzleDataChange(vs_swizzle_write_offset, value); - vs_swizzle_write_offset++; + VertexShader::SubmitSwizzleDataChange(registers.vs_swizzle_patterns.offset, value); + registers.vs_swizzle_patterns.offset++; break; } diff --git a/src/video_core/pica.h b/src/video_core/pica.h index 9c1a12dc..cf9dc485 100644 --- a/src/video_core/pica.h +++ b/src/video_core/pica.h @@ -678,7 +678,9 @@ struct Regs { INSERT_PADDING_WORDS(0x2); struct { - u32 begin_load; + // Offset of the next instruction to write code to. + // Incremented with each instruction write. + u32 offset; // Writing to these registers sets the "current" word in the shader program. // TODO: It's not clear how the hardware stores what the "current" word is. @@ -690,7 +692,9 @@ struct Regs { // This register group is used to load an internal table of swizzling patterns, // which are indexed by each shader instruction to specify vector component swizzling. struct { - u32 begin_load; + // Offset of the next swizzle pattern to write code to. + // Incremented with each instruction write. + u32 offset; // Writing to these registers sets the "current" swizzle pattern in the table. // TODO: It's not clear how the hardware stores what the "current" swizzle pattern is. -- cgit v1.2.3