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-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp3
-rw-r--r--src/core/hle/service/am/am.cpp1
-rw-r--r--src/core/hw/y2r.cpp1
3 files changed, 2 insertions, 3 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 0c20c2bc..bb0cbb4d 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -3886,7 +3886,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
#endif
arm_inst* inst_base;
unsigned int addr;
- unsigned int phys_addr;
unsigned int num_instrs = 0;
int ptr;
@@ -3905,8 +3904,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
else
cpu->Reg[15] &= 0xfffffffc;
- phys_addr = cpu->Reg[15];
-
// Find the cached instruction cream, otherwise translate it...
auto itr = cpu->instruction_cache.find(cpu->Reg[15]);
if (itr != cpu->instruction_cache.end()) {
diff --git a/src/core/hle/service/am/am.cpp b/src/core/hle/service/am/am.cpp
index 7332478f..64f3bc7e 100644
--- a/src/core/hle/service/am/am.cpp
+++ b/src/core/hle/service/am/am.cpp
@@ -5,6 +5,7 @@
#include "common/logging/log.h"
#include "core/hle/service/service.h"
+#include "core/hle/service/am/am.h"
#include "core/hle/service/am/am_app.h"
#include "core/hle/service/am/am_net.h"
#include "core/hle/service/am/am_sys.h"
diff --git a/src/core/hw/y2r.cpp b/src/core/hw/y2r.cpp
index f80e26ec..082a4db8 100644
--- a/src/core/hw/y2r.cpp
+++ b/src/core/hw/y2r.cpp
@@ -14,6 +14,7 @@
#include "common/vector_math.h"
#include "core/hle/service/y2r_u.h"
+#include "core/hw/y2r.h"
#include "core/memory.h"
namespace HW {