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-rw-r--r--src/core/arm/skyeye_common/vfp/vfp.cpp38
-rw-r--r--src/core/arm/skyeye_common/vfp/vfp.h14
-rw-r--r--src/core/arm/skyeye_common/vfp/vfp_helper.h4
-rw-r--r--src/core/arm/skyeye_common/vfp/vfpdouble.cpp12
-rw-r--r--src/core/arm/skyeye_common/vfp/vfpinstr.cpp197
-rw-r--r--src/core/arm/skyeye_common/vfp/vfpsingle.cpp4
6 files changed, 139 insertions, 130 deletions
diff --git a/src/core/arm/skyeye_common/vfp/vfp.cpp b/src/core/arm/skyeye_common/vfp/vfp.cpp
index 571d6c2f..26f303de 100644
--- a/src/core/arm/skyeye_common/vfp/vfp.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfp.cpp
@@ -20,39 +20,30 @@
/* Note: this file handles interface with arm core and vfp registers */
+#include "common/common_funcs.h"
#include "common/logging/log.h"
-#include "core/arm/skyeye_common/armdefs.h"
+#include "core/arm/skyeye_common/armstate.h"
#include "core/arm/skyeye_common/vfp/asm_vfp.h"
#include "core/arm/skyeye_common/vfp/vfp.h"
-unsigned VFPInit(ARMul_State* state)
+void VFPInit(ARMul_State* state)
{
state->VFP[VFP_FPSID] = VFP_FPSID_IMPLMEN<<24 | VFP_FPSID_SW<<23 | VFP_FPSID_SUBARCH<<16 |
VFP_FPSID_PARTNUM<<8 | VFP_FPSID_VARIANT<<4 | VFP_FPSID_REVISION;
state->VFP[VFP_FPEXC] = 0;
state->VFP[VFP_FPSCR] = 0;
+ // ARM11 MPCore instruction register reset values.
+ state->VFP[VFP_FPINST] = 0xEE000A00;
+ state->VFP[VFP_FPINST2] = 0;
+
// ARM11 MPCore feature register values.
state->VFP[VFP_MVFR0] = 0x11111111;
state->VFP[VFP_MVFR1] = 0;
-
- return 0;
-}
-
-void VMSR(ARMul_State* state, ARMword reg, ARMword Rt)
-{
- if (reg == 1)
- {
- state->VFP[VFP_FPSCR] = state->Reg[Rt];
- }
- else if (reg == 8)
- {
- state->VFP[VFP_FPEXC] = state->Reg[Rt];
- }
}
-void VMOVBRS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword n, ARMword* value)
+void VMOVBRS(ARMul_State* state, u32 to_arm, u32 t, u32 n, u32* value)
{
if (to_arm)
{
@@ -64,7 +55,7 @@ void VMOVBRS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword n, ARMword*
}
}
-void VMOVBRRD(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2)
+void VMOVBRRD(ARMul_State* state, u32 to_arm, u32 t, u32 t2, u32 n, u32* value1, u32* value2)
{
if (to_arm)
{
@@ -77,7 +68,7 @@ void VMOVBRRD(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword
state->ExtReg[n*2] = *value1;
}
}
-void VMOVBRRSS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2)
+void VMOVBRRSS(ARMul_State* state, u32 to_arm, u32 t, u32 t2, u32 n, u32* value1, u32* value2)
{
if (to_arm)
{
@@ -91,7 +82,7 @@ void VMOVBRRSS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMwor
}
}
-void VMOVI(ARMul_State* state, ARMword single, ARMword d, ARMword imm)
+void VMOVI(ARMul_State* state, u32 single, u32 d, u32 imm)
{
if (single)
{
@@ -104,7 +95,7 @@ void VMOVI(ARMul_State* state, ARMword single, ARMword d, ARMword imm)
state->ExtReg[d*2] = 0;
}
}
-void VMOVR(ARMul_State* state, ARMword single, ARMword d, ARMword m)
+void VMOVR(ARMul_State* state, u32 single, u32 d, u32 m)
{
if (single)
{
@@ -153,9 +144,8 @@ void vfp_raise_exceptions(ARMul_State* state, u32 exceptions, u32 inst, u32 fpsc
LOG_TRACE(Core_ARM11, "VFP: raising exceptions %08x\n", exceptions);
if (exceptions == VFP_EXCEPTION_ERROR) {
- LOG_TRACE(Core_ARM11, "unhandled bounce %x\n", inst);
- exit(-1);
- return;
+ LOG_CRITICAL(Core_ARM11, "unhandled bounce %x\n", inst);
+ Crash();
}
/*
diff --git a/src/core/arm/skyeye_common/vfp/vfp.h b/src/core/arm/skyeye_common/vfp/vfp.h
index acefae9b..88908da9 100644
--- a/src/core/arm/skyeye_common/vfp/vfp.h
+++ b/src/core/arm/skyeye_common/vfp/vfp.h
@@ -26,7 +26,7 @@
#define CHECK_VFP_ENABLED
#define CHECK_VFP_CDP_RET vfp_raise_exceptions(cpu, ret, inst_cream->instr, cpu->VFP[VFP_FPSCR]);
-unsigned VFPInit(ARMul_State* state);
+void VFPInit(ARMul_State* state);
s32 vfp_get_float(ARMul_State* state, u32 reg);
void vfp_put_float(ARMul_State* state, s32 val, u32 reg);
@@ -36,10 +36,8 @@ void vfp_raise_exceptions(ARMul_State* state, u32 exceptions, u32 inst, u32 fpsc
u32 vfp_single_cpdo(ARMul_State* state, u32 inst, u32 fpscr);
u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr);
-void VMSR(ARMul_State* state, ARMword reg, ARMword Rt);
-void VMOVBRS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword n, ARMword* value);
-void VMOVBRRD(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2);
-void VMOVBRRSS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2);
-void VMOVI(ARMul_State* state, ARMword single, ARMword d, ARMword imm);
-void VMOVR(ARMul_State* state, ARMword single, ARMword d, ARMword imm);
-
+void VMOVBRS(ARMul_State* state, u32 to_arm, u32 t, u32 n, u32* value);
+void VMOVBRRD(ARMul_State* state, u32 to_arm, u32 t, u32 t2, u32 n, u32* value1, u32* value2);
+void VMOVBRRSS(ARMul_State* state, u32 to_arm, u32 t, u32 t2, u32 n, u32* value1, u32* value2);
+void VMOVI(ARMul_State* state, u32 single, u32 d, u32 imm);
+void VMOVR(ARMul_State* state, u32 single, u32 d, u32 imm);
diff --git a/src/core/arm/skyeye_common/vfp/vfp_helper.h b/src/core/arm/skyeye_common/vfp/vfp_helper.h
index 2007d6dc..91a8d4d5 100644
--- a/src/core/arm/skyeye_common/vfp/vfp_helper.h
+++ b/src/core/arm/skyeye_common/vfp/vfp_helper.h
@@ -34,7 +34,7 @@
#include <cstdio>
#include "common/common_types.h"
-#include "core/arm/skyeye_common/armdefs.h"
+#include "core/arm/skyeye_common/armstate.h"
#include "core/arm/skyeye_common/vfp/asm_vfp.h"
#define do_div(n, base) {n/=base;}
@@ -415,7 +415,7 @@ struct op {
u32 flags;
};
-static inline u32 fls(ARMword x)
+static inline u32 fls(u32 x)
{
int r = 32;
diff --git a/src/core/arm/skyeye_common/vfp/vfpdouble.cpp b/src/core/arm/skyeye_common/vfp/vfpdouble.cpp
index f9104958..1d844a66 100644
--- a/src/core/arm/skyeye_common/vfp/vfpdouble.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfpdouble.cpp
@@ -70,9 +70,9 @@ static void vfp_double_dump(const char *str, struct vfp_double *d)
static void vfp_double_normalise_denormal(struct vfp_double *vd)
{
- int bits = 31 - fls((ARMword)(vd->significand >> 32));
+ int bits = 31 - fls((u32)(vd->significand >> 32));
if (bits == 31)
- bits = 63 - fls((ARMword)vd->significand);
+ bits = 63 - fls((u32)vd->significand);
vfp_double_dump("normalise_denormal: in", vd);
@@ -109,9 +109,9 @@ u32 vfp_double_normaliseround(ARMul_State* state, int dd, struct vfp_double *vd,
exponent = vd->exponent;
significand = vd->significand;
- shift = 32 - fls((ARMword)(significand >> 32));
+ shift = 32 - fls((u32)(significand >> 32));
if (shift == 32)
- shift = 64 - fls((ARMword)significand);
+ shift = 64 - fls((u32)significand);
if (shift) {
exponent -= shift;
significand <<= shift;
@@ -566,7 +566,7 @@ static u32 vfp_double_ftoui(ARMul_State* state, int sd, int unused, int dm, u32
/*
* 2^0 <= m < 2^32-2^8
*/
- d = (ARMword)((vdm.significand << 1) >> shift);
+ d = (u32)((vdm.significand << 1) >> shift);
rem = vdm.significand << (65 - shift);
if (rmode == FPSCR_ROUND_NEAREST) {
@@ -647,7 +647,7 @@ static u32 vfp_double_ftosi(ARMul_State* state, int sd, int unused, int dm, u32
int shift = 1023 + 63 - vdm.exponent; /* 58 */
u64 rem, incr = 0;
- d = (ARMword)((vdm.significand << 1) >> shift);
+ d = (u32)((vdm.significand << 1) >> shift);
rem = vdm.significand << (65 - shift);
if (rmode == FPSCR_ROUND_NEAREST) {
diff --git a/src/core/arm/skyeye_common/vfp/vfpinstr.cpp b/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
index 67fe63aa..9b99fc5b 100644
--- a/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
@@ -51,7 +51,7 @@ VMLA_INST:
CHECK_VFP_CDP_RET;
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vmla_inst));
FETCH_INST;
GOTO_NEXT_INST;
@@ -100,7 +100,7 @@ VMLS_INST:
CHECK_VFP_CDP_RET;
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vmls_inst));
FETCH_INST;
GOTO_NEXT_INST;
@@ -149,7 +149,7 @@ VNMLA_INST:
CHECK_VFP_CDP_RET;
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vnmla_inst));
FETCH_INST;
GOTO_NEXT_INST;
@@ -199,7 +199,7 @@ VNMLS_INST:
CHECK_VFP_CDP_RET;
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vnmls_inst));
FETCH_INST;
GOTO_NEXT_INST;
@@ -248,7 +248,7 @@ VNMUL_INST:
CHECK_VFP_CDP_RET;
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vnmul_inst));
FETCH_INST;
GOTO_NEXT_INST;
@@ -297,7 +297,7 @@ VMUL_INST:
CHECK_VFP_CDP_RET;
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vmul_inst));
FETCH_INST;
GOTO_NEXT_INST;
@@ -346,7 +346,7 @@ VADD_INST:
CHECK_VFP_CDP_RET;
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vadd_inst));
FETCH_INST;
GOTO_NEXT_INST;
@@ -395,7 +395,7 @@ VSUB_INST:
CHECK_VFP_CDP_RET;
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vsub_inst));
FETCH_INST;
GOTO_NEXT_INST;
@@ -444,7 +444,7 @@ VDIV_INST:
CHECK_VFP_CDP_RET;
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vdiv_inst));
FETCH_INST;
GOTO_NEXT_INST;
@@ -492,7 +492,7 @@ VMOVI_INST:
VMOVI(cpu, inst_cream->single, inst_cream->d, inst_cream->imm);
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vmovi_inst));
FETCH_INST;
GOTO_NEXT_INST;
@@ -536,7 +536,7 @@ VMOVR_INST:
VMOVR(cpu, inst_cream->single, inst_cream->d, inst_cream->m);
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vmovr_inst));
FETCH_INST;
GOTO_NEXT_INST;
@@ -585,7 +585,7 @@ VABS_INST:
CHECK_VFP_CDP_RET;
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vabs_inst));
FETCH_INST;
GOTO_NEXT_INST;
@@ -635,7 +635,7 @@ VNEG_INST:
CHECK_VFP_CDP_RET;
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vneg_inst));
FETCH_INST;
GOTO_NEXT_INST;
@@ -684,7 +684,7 @@ VSQRT_INST:
CHECK_VFP_CDP_RET;
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vsqrt_inst));
FETCH_INST;
GOTO_NEXT_INST;
@@ -733,7 +733,7 @@ VCMP_INST:
CHECK_VFP_CDP_RET;
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vcmp_inst));
FETCH_INST;
GOTO_NEXT_INST;
@@ -782,7 +782,7 @@ VCMP2_INST:
CHECK_VFP_CDP_RET;
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vcmp2_inst));
FETCH_INST;
GOTO_NEXT_INST;
@@ -831,7 +831,7 @@ VCVTBDS_INST:
CHECK_VFP_CDP_RET;
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vcvtbds_inst));
FETCH_INST;
GOTO_NEXT_INST;
@@ -882,7 +882,7 @@ VCVTBFF_INST:
CHECK_VFP_CDP_RET;
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vcvtbff_inst));
FETCH_INST;
GOTO_NEXT_INST;
@@ -931,7 +931,7 @@ VCVTBFI_INST:
CHECK_VFP_CDP_RET;
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vcvtbfi_inst));
FETCH_INST;
GOTO_NEXT_INST;
@@ -981,7 +981,7 @@ VMOVBRS_INST:
VMOVBRS(cpu, inst_cream->to_arm, inst_cream->t, inst_cream->n, &(cpu->Reg[inst_cream->t]));
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vmovbrs_inst));
FETCH_INST;
GOTO_NEXT_INST;
@@ -995,7 +995,7 @@ VMOVBRS_INST:
#ifdef VFP_INTERPRETER_STRUCT
struct vmsr_inst {
unsigned int reg;
- unsigned int Rd;
+ unsigned int Rt;
};
#endif
#ifdef VFP_INTERPRETER_TRANS
@@ -1009,7 +1009,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vmsr)(unsigned int inst, int index)
inst_base->br = NON_BRANCH;
inst_cream->reg = BITS(inst, 16, 19);
- inst_cream->Rd = BITS(inst, 12, 15);
+ inst_cream->Rt = BITS(inst, 12, 15);
return inst_base;
}
@@ -1017,17 +1017,32 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vmsr)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VMSR_INST:
{
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
/* FIXME: special case for access to FPSID and FPEXC, VFP must be disabled ,
and in privileged mode */
/* Exceptions must be checked, according to v7 ref manual */
CHECK_VFP_ENABLED;
- vmsr_inst *inst_cream = (vmsr_inst *)inst_base->component;
+ vmsr_inst* const inst_cream = (vmsr_inst*)inst_base->component;
+
+ unsigned int reg = inst_cream->reg;
+ unsigned int rt = inst_cream->Rt;
- VMSR(cpu, inst_cream->reg, inst_cream->Rd);
+ if (reg == 1)
+ {
+ cpu->VFP[VFP_FPSCR] = cpu->Reg[rt];
+ }
+ else if (cpu->InAPrivilegedMode())
+ {
+ if (reg == 8)
+ cpu->VFP[VFP_FPEXC] = cpu->Reg[rt];
+ else if (reg == 9)
+ cpu->VFP[VFP_FPINST] = cpu->Reg[rt];
+ else if (reg == 10)
+ cpu->VFP[VFP_FPINST2] = cpu->Reg[rt];
+ }
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vmsr_inst));
FETCH_INST;
GOTO_NEXT_INST;
@@ -1075,7 +1090,7 @@ VMOVBRC_INST:
cpu->ExtReg[(2 * inst_cream->d) + inst_cream->index] = cpu->Reg[inst_cream->t];
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vmovbrc_inst));
FETCH_INST;
GOTO_NEXT_INST;
@@ -1111,19 +1126,22 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(vmrs)(unsigned int inst, int index)
#ifdef VFP_INTERPRETER_IMPL
VMRS_INST:
{
- if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
+ if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
/* FIXME: special case for access to FPSID and FPEXC, VFP must be disabled,
and in privileged mode */
/* Exceptions must be checked, according to v7 ref manual */
CHECK_VFP_ENABLED;
- vmrs_inst *inst_cream = (vmrs_inst *)inst_base->component;
+ vmrs_inst* const inst_cream = (vmrs_inst*)inst_base->component;
- if (inst_cream->reg == 1) /* FPSCR */
+ unsigned int reg = inst_cream->reg;
+ unsigned int rt = inst_cream->Rt;
+
+ if (reg == 1) // FPSCR
{
- if (inst_cream->Rt != 15)
+ if (rt != 15)
{
- cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_FPSCR];
+ cpu->Reg[rt] = cpu->VFP[VFP_FPSCR];
}
else
{
@@ -1133,28 +1151,29 @@ VMRS_INST:
cpu->VFlag = (cpu->VFP[VFP_FPSCR] >> 28) & 1;
}
}
- else
+ else if (reg == 0)
{
- switch (inst_cream->reg)
- {
- case 0:
- cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_FPSID];
- break;
- case 6:
- cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_MVFR1];
- break;
- case 7:
- cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_MVFR0];
- break;
- case 8:
- cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_FPEXC];
- break;
- default:
- break;
- }
+ cpu->Reg[rt] = cpu->VFP[VFP_FPSID];
+ }
+ else if (reg == 6)
+ {
+ cpu->Reg[rt] = cpu->VFP[VFP_MVFR1];
+ }
+ else if (reg == 7)
+ {
+ cpu->Reg[rt] = cpu->VFP[VFP_MVFR0];
+ }
+ else if (cpu->InAPrivilegedMode())
+ {
+ if (reg == 8)
+ cpu->Reg[rt] = cpu->VFP[VFP_FPEXC];
+ else if (reg == 9)
+ cpu->Reg[rt] = cpu->VFP[VFP_FPINST];
+ else if (reg == 10)
+ cpu->Reg[rt] = cpu->VFP[VFP_FPINST2];
}
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vmrs_inst));
FETCH_INST;
GOTO_NEXT_INST;
@@ -1202,7 +1221,7 @@ VMOVBCR_INST:
cpu->Reg[inst_cream->t] = cpu->ExtReg[(2 * inst_cream->d) + inst_cream->index];
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vmovbcr_inst));
FETCH_INST;
GOTO_NEXT_INST;
@@ -1255,7 +1274,7 @@ VMOVBRRSS_INST:
VMOVBRRSS(cpu, inst_cream->to_arm, inst_cream->t, inst_cream->t2, inst_cream->m,
&cpu->Reg[inst_cream->t], &cpu->Reg[inst_cream->t2]);
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vmovbrrss_inst));
FETCH_INST;
GOTO_NEXT_INST;
@@ -1303,7 +1322,7 @@ VMOVBRRD_INST:
VMOVBRRD(cpu, inst_cream->to_arm, inst_cream->t, inst_cream->t2, inst_cream->m,
&(cpu->Reg[inst_cream->t]), &(cpu->Reg[inst_cream->t2]));
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vmovbrrd_inst));
FETCH_INST;
GOTO_NEXT_INST;
@@ -1359,23 +1378,23 @@ VSTR_INST:
if (inst_cream->single)
{
- WriteMemory32(cpu, addr, cpu->ExtReg[inst_cream->d]);
+ cpu->WriteMemory32(addr, cpu->ExtReg[inst_cream->d]);
}
else
{
const u32 word1 = cpu->ExtReg[inst_cream->d*2+0];
const u32 word2 = cpu->ExtReg[inst_cream->d*2+1];
- if (InBigEndianMode(cpu)) {
- WriteMemory32(cpu, addr + 0, word2);
- WriteMemory32(cpu, addr + 4, word1);
+ if (cpu->InBigEndianMode()) {
+ cpu->WriteMemory32(addr + 0, word2);
+ cpu->WriteMemory32(addr + 4, word1);
} else {
- WriteMemory32(cpu, addr + 0, word1);
- WriteMemory32(cpu, addr + 4, word2);
+ cpu->WriteMemory32(addr + 0, word1);
+ cpu->WriteMemory32(addr + 4, word2);
}
}
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vstr_inst));
FETCH_INST;
GOTO_NEXT_INST;
@@ -1425,7 +1444,7 @@ VPUSH_INST:
{
if (inst_cream->single)
{
- WriteMemory32(cpu, addr, cpu->ExtReg[inst_cream->d+i]);
+ cpu->WriteMemory32(addr, cpu->ExtReg[inst_cream->d+i]);
addr += 4;
}
else
@@ -1433,12 +1452,12 @@ VPUSH_INST:
const u32 word1 = cpu->ExtReg[(inst_cream->d+i)*2+0];
const u32 word2 = cpu->ExtReg[(inst_cream->d+i)*2+1];
- if (InBigEndianMode(cpu)) {
- WriteMemory32(cpu, addr + 0, word2);
- WriteMemory32(cpu, addr + 4, word1);
+ if (cpu->InBigEndianMode()) {
+ cpu->WriteMemory32(addr + 0, word2);
+ cpu->WriteMemory32(addr + 4, word1);
} else {
- WriteMemory32(cpu, addr + 0, word1);
- WriteMemory32(cpu, addr + 4, word2);
+ cpu->WriteMemory32(addr + 0, word1);
+ cpu->WriteMemory32(addr + 4, word2);
}
addr += 8;
@@ -1447,7 +1466,7 @@ VPUSH_INST:
cpu->Reg[R13] -= inst_cream->imm32;
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vpush_inst));
FETCH_INST;
GOTO_NEXT_INST;
@@ -1503,7 +1522,7 @@ VSTM_INST: /* encoding 1 */
{
if (inst_cream->single)
{
- WriteMemory32(cpu, addr, cpu->ExtReg[inst_cream->d+i]);
+ cpu->WriteMemory32(addr, cpu->ExtReg[inst_cream->d+i]);
addr += 4;
}
else
@@ -1511,12 +1530,12 @@ VSTM_INST: /* encoding 1 */
const u32 word1 = cpu->ExtReg[(inst_cream->d+i)*2+0];
const u32 word2 = cpu->ExtReg[(inst_cream->d+i)*2+1];
- if (InBigEndianMode(cpu)) {
- WriteMemory32(cpu, addr + 0, word2);
- WriteMemory32(cpu, addr + 4, word1);
+ if (cpu->InBigEndianMode()) {
+ cpu->WriteMemory32(addr + 0, word2);
+ cpu->WriteMemory32(addr + 4, word1);
} else {
- WriteMemory32(cpu, addr + 0, word1);
- WriteMemory32(cpu, addr + 4, word2);
+ cpu->WriteMemory32(addr + 0, word1);
+ cpu->WriteMemory32(addr + 4, word2);
}
addr += 8;
@@ -1578,15 +1597,15 @@ VPOP_INST:
{
if (inst_cream->single)
{
- cpu->ExtReg[inst_cream->d+i] = ReadMemory32(cpu, addr);
+ cpu->ExtReg[inst_cream->d+i] = cpu->ReadMemory32(addr);
addr += 4;
}
else
{
- const u32 word1 = ReadMemory32(cpu, addr + 0);
- const u32 word2 = ReadMemory32(cpu, addr + 4);
+ const u32 word1 = cpu->ReadMemory32(addr + 0);
+ const u32 word2 = cpu->ReadMemory32(addr + 4);
- if (InBigEndianMode(cpu)) {
+ if (cpu->InBigEndianMode()) {
cpu->ExtReg[(inst_cream->d+i)*2+0] = word2;
cpu->ExtReg[(inst_cream->d+i)*2+1] = word1;
} else {
@@ -1599,7 +1618,7 @@ VPOP_INST:
}
cpu->Reg[R13] += inst_cream->imm32;
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vpop_inst));
FETCH_INST;
GOTO_NEXT_INST;
@@ -1651,14 +1670,14 @@ VLDR_INST:
if (inst_cream->single)
{
- cpu->ExtReg[inst_cream->d] = ReadMemory32(cpu, addr);
+ cpu->ExtReg[inst_cream->d] = cpu->ReadMemory32(addr);
}
else
{
- const u32 word1 = ReadMemory32(cpu, addr + 0);
- const u32 word2 = ReadMemory32(cpu, addr + 4);
+ const u32 word1 = cpu->ReadMemory32(addr + 0);
+ const u32 word2 = cpu->ReadMemory32(addr + 4);
- if (InBigEndianMode(cpu)) {
+ if (cpu->InBigEndianMode()) {
cpu->ExtReg[inst_cream->d*2+0] = word2;
cpu->ExtReg[inst_cream->d*2+1] = word1;
} else {
@@ -1667,7 +1686,7 @@ VLDR_INST:
}
}
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vldr_inst));
FETCH_INST;
GOTO_NEXT_INST;
@@ -1723,15 +1742,15 @@ VLDM_INST:
{
if (inst_cream->single)
{
- cpu->ExtReg[inst_cream->d+i] = ReadMemory32(cpu, addr);
+ cpu->ExtReg[inst_cream->d+i] = cpu->ReadMemory32(addr);
addr += 4;
}
else
{
- const u32 word1 = ReadMemory32(cpu, addr + 0);
- const u32 word2 = ReadMemory32(cpu, addr + 4);
+ const u32 word1 = cpu->ReadMemory32(addr + 0);
+ const u32 word2 = cpu->ReadMemory32(addr + 4);
- if (InBigEndianMode(cpu)) {
+ if (cpu->InBigEndianMode()) {
cpu->ExtReg[(inst_cream->d+i)*2+0] = word2;
cpu->ExtReg[(inst_cream->d+i)*2+1] = word1;
} else {
@@ -1747,7 +1766,7 @@ VLDM_INST:
cpu->Reg[inst_cream->n] - inst_cream->imm32);
}
}
- cpu->Reg[15] += GET_INST_SIZE(cpu);
+ cpu->Reg[15] += cpu->GetInstructionSize();
INC_PC(sizeof(vldm_inst));
FETCH_INST;
GOTO_NEXT_INST;
diff --git a/src/core/arm/skyeye_common/vfp/vfpsingle.cpp b/src/core/arm/skyeye_common/vfp/vfpsingle.cpp
index 5a655a6f..e5d33925 100644
--- a/src/core/arm/skyeye_common/vfp/vfpsingle.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfpsingle.cpp
@@ -53,6 +53,8 @@
#include <cinttypes>
+#include "common/common_funcs.h"
+#include "common/common_types.h"
#include "common/logging/log.h"
#include "core/arm/skyeye_common/vfp/vfp_helper.h"
@@ -1246,7 +1248,7 @@ u32 vfp_single_cpdo(ARMul_State* state, u32 inst, u32 fpscr)
if (!fop->fn) {
LOG_CRITICAL(Core_ARM11, "could not find single op %d, inst=0x%x@0x%x", FEXT_TO_IDX(inst), inst, state->Reg[15]);
- exit(-1);
+ Crash();
goto invalid;
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-29 14:50:02 +0000