diff options
Diffstat (limited to 'src/core/arm/interpreter/armsupp.cpp')
| -rw-r--r-- | src/core/arm/interpreter/armsupp.cpp | 428 |
1 files changed, 428 insertions, 0 deletions
diff --git a/src/core/arm/interpreter/armsupp.cpp b/src/core/arm/interpreter/armsupp.cpp index aca2bfbb..1b078dc7 100644 --- a/src/core/arm/interpreter/armsupp.cpp +++ b/src/core/arm/interpreter/armsupp.cpp @@ -15,7 +15,11 @@ along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +#include "common/logging/log.h" + +#include "core/mem_map.h" #include "core/arm/skyeye_common/armdefs.h" +#include "core/arm/skyeye_common/arm_regformat.h" // Unsigned sum of absolute difference u8 ARMul_UnsignedAbsoluteDifference(u8 left, u8 right) @@ -207,3 +211,427 @@ bool InBigEndianMode(ARMul_State* cpu) { return (cpu->Cpsr & (1 << 9)) != 0; } + +// Whether or not the given CPU is in a mode other than user mode. +bool InAPrivilegedMode(ARMul_State* cpu) +{ + return (cpu->Mode != USER32MODE); +} + +// Reads from the CP15 registers. Used with implementation of the MRC instruction. +// Note that since the 3DS does not have the hypervisor extensions, these registers +// are not implemented. +u32 ReadCP15Register(ARMul_State* cpu, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2) +{ + // Unprivileged registers + if (crn == 13 && opcode_1 == 0 && crm == 0) + { + if (opcode_2 == 2) + return cpu->CP15[CP15_THREAD_UPRW]; + + if (opcode_2 == 3) + return cpu->CP15[CP15_THREAD_URO]; + } + + if (InAPrivilegedMode(cpu)) + { + if (crn == 0 && opcode_1 == 0) + { + if (crm == 0) + { + if (opcode_2 == 0) + return cpu->CP15[CP15_MAIN_ID]; + + if (opcode_2 == 1) + return cpu->CP15[CP15_CACHE_TYPE]; + + if (opcode_2 == 3) + return cpu->CP15[CP15_TLB_TYPE]; + + if (opcode_2 == 5) + return cpu->CP15[CP15_CPU_ID]; + } + else if (crm == 1) + { + if (opcode_2 == 0) + return cpu->CP15[CP15_PROCESSOR_FEATURE_0]; + + if (opcode_2 == 1) + return cpu->CP15[CP15_PROCESSOR_FEATURE_1]; + + if (opcode_2 == 2) + return cpu->CP15[CP15_DEBUG_FEATURE_0]; + + if (opcode_2 == 4) + return cpu->CP15[CP15_MEMORY_MODEL_FEATURE_0]; + + if (opcode_2 == 5) + return cpu->CP15[CP15_MEMORY_MODEL_FEATURE_1]; + + if (opcode_2 == 6) + return cpu->CP15[CP15_MEMORY_MODEL_FEATURE_2]; + + if (opcode_2 == 7) + return cpu->CP15[CP15_MEMORY_MODEL_FEATURE_3]; + } + else if (crm == 2) + { + if (opcode_2 == 0) + return cpu->CP15[CP15_ISA_FEATURE_0]; + + if (opcode_2 == 1) + return cpu->CP15[CP15_ISA_FEATURE_1]; + + if (opcode_2 == 2) + return cpu->CP15[CP15_ISA_FEATURE_2]; + + if (opcode_2 == 3) + return cpu->CP15[CP15_ISA_FEATURE_3]; + + if (opcode_2 == 4) + return cpu->CP15[CP15_ISA_FEATURE_4]; + } + } + + if (crn == 1 && opcode_1 == 0 && crm == 0) + { + if (opcode_2 == 0) + return cpu->CP15[CP15_CONTROL]; + + if (opcode_2 == 1) + return cpu->CP15[CP15_AUXILIARY_CONTROL]; + + if (opcode_2 == 2) + return cpu->CP15[CP15_COPROCESSOR_ACCESS_CONTROL]; + } + + if (crn == 2 && opcode_1 == 0 && crm == 0) + { + if (opcode_2 == 0) + return cpu->CP15[CP15_TRANSLATION_BASE_TABLE_0]; + + if (opcode_2 == 1) + return cpu->CP15[CP15_TRANSLATION_BASE_TABLE_1]; + + if (opcode_2 == 2) + return cpu->CP15[CP15_TRANSLATION_BASE_CONTROL]; + } + + if (crn == 3 && opcode_1 == 0 && crm == 0 && opcode_2 == 0) + return cpu->CP15[CP15_DOMAIN_ACCESS_CONTROL]; + + if (crn == 5 && opcode_1 == 0 && crm == 0) + { + if (opcode_2 == 0) + return cpu->CP15[CP15_FAULT_STATUS]; + + if (opcode_2 == 1) + return cpu->CP15[CP15_INSTR_FAULT_STATUS]; + } + + if (crn == 6 && opcode_1 == 0 && crm == 0) + { + if (opcode_2 == 0) + return cpu->CP15[CP15_FAULT_ADDRESS]; + + if (opcode_2 == 1) + return cpu->CP15[CP15_WFAR]; + } + + if (crn == 7 && opcode_1 == 0 && crm == 4 && opcode_2 == 0) + return cpu->CP15[CP15_PHYS_ADDRESS]; + + if (crn == 9 && opcode_1 == 0 && crm == 0 && opcode_2 == 0) + return cpu->CP15[CP15_DATA_CACHE_LOCKDOWN]; + + if (crn == 10 && opcode_1 == 0) + { + if (crm == 0 && opcode_2 == 0) + return cpu->CP15[CP15_TLB_LOCKDOWN]; + + if (crm == 2) + { + if (opcode_2 == 0) + return cpu->CP15[CP15_PRIMARY_REGION_REMAP]; + + if (opcode_2 == 1) + return cpu->CP15[CP15_NORMAL_REGION_REMAP]; + } + } + + if (crn == 13 && crm == 0) + { + if (opcode_2 == 0) + return cpu->CP15[CP15_PID]; + + if (opcode_2 == 1) + return cpu->CP15[CP15_CONTEXT_ID]; + + if (opcode_2 == 4) + return cpu->CP15[CP15_THREAD_PRW]; + } + + if (crn == 15) + { + if (opcode_1 == 0 && crm == 12) + { + if (opcode_2 == 0) + return cpu->CP15[CP15_PERFORMANCE_MONITOR_CONTROL]; + + if (opcode_2 == 1) + return cpu->CP15[CP15_CYCLE_COUNTER]; + + if (opcode_2 == 2) + return cpu->CP15[CP15_COUNT_0]; + + if (opcode_2 == 3) + return cpu->CP15[CP15_COUNT_1]; + } + + if (opcode_1 == 5 && opcode_2 == 2) + { + if (crm == 5) + return cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS]; + + if (crm == 6) + return cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS]; + + if (crm == 7) + return cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE]; + } + + if (opcode_1 == 7 && crm == 1 && opcode_2 == 0) + return cpu->CP15[CP15_TLB_DEBUG_CONTROL]; + } + } + + LOG_ERROR(Core_ARM11, "MRC CRn=%u, CRm=%u, OP1=%u OP2=%u is not implemented. Returning zero.", crn, crm, opcode_1, opcode_2); + return 0; +} + +// Write to the CP15 registers. Used with implementation of the MCR instruction. +// Note that since the 3DS does not have the hypervisor extensions, these registers +// are not implemented. +void WriteCP15Register(ARMul_State* cpu, u32 value, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2) +{ + if (InAPrivilegedMode(cpu)) + { + if (crn == 1 && opcode_1 == 0 && crm == 0) + { + if (opcode_2 == 0) + cpu->CP15[CP15_CONTROL] = value; + else if (opcode_2 == 1) + cpu->CP15[CP15_AUXILIARY_CONTROL] = value; + else if (opcode_2 == 2) + cpu->CP15[CP15_COPROCESSOR_ACCESS_CONTROL] = value; + } + else if (crn == 2 && opcode_1 == 0 && crm == 0) + { + if (opcode_2 == 0) + cpu->CP15[CP15_TRANSLATION_BASE_TABLE_0] = value; + else if (opcode_2 == 1) + cpu->CP15[CP15_TRANSLATION_BASE_TABLE_1] = value; + else if (opcode_2 == 2) + cpu->CP15[CP15_TRANSLATION_BASE_CONTROL] = value; + } + else if (crn == 3 && opcode_1 == 0 && crm == 0 && opcode_2 == 0) + { + cpu->CP15[CP15_DOMAIN_ACCESS_CONTROL] = value; + } + else if (crn == 5 && opcode_1 == 0 && crm == 0) + { + if (opcode_2 == 0) + cpu->CP15[CP15_FAULT_STATUS] = value; + else if (opcode_2 == 1) + cpu->CP15[CP15_INSTR_FAULT_STATUS] = value; + } + else if (crn == 6 && opcode_1 == 0 && crm == 0) + { + if (opcode_2 == 0) + cpu->CP15[CP15_FAULT_ADDRESS] = value; + else if (opcode_2 == 1) + cpu->CP15[CP15_WFAR] = value; + } + else if (crn == 7 && opcode_1 == 0) + { + if (crm == 0 && opcode_2 == 4) + { + cpu->CP15[CP15_WAIT_FOR_INTERRUPT] = value; + } + else if (crm == 4 && opcode_2 == 0) + { + // NOTE: Not entirely accurate. This should do permission checks. + cpu->CP15[CP15_PHYS_ADDRESS] = Memory::VirtualToPhysicalAddress(value); + } + else if (crm == 5) + { + if (opcode_2 == 0) + cpu->CP15[CP15_INVALIDATE_INSTR_CACHE] = value; + else if (opcode_2 == 1) + cpu->CP15[CP15_INVALIDATE_INSTR_CACHE_USING_MVA] = value; + else if (opcode_2 == 2) + cpu->CP15[CP15_INVALIDATE_INSTR_CACHE_USING_INDEX] = value; + else if (opcode_2 == 6) + cpu->CP15[CP15_FLUSH_BRANCH_TARGET_CACHE] = value; + else if (opcode_2 == 7) + cpu->CP15[CP15_FLUSH_BRANCH_TARGET_CACHE_ENTRY] = value; + } + else if (crm == 6) + { + if (opcode_2 == 0) + cpu->CP15[CP15_INVALIDATE_DATA_CACHE] = value; + else if (opcode_2 == 1) + cpu->CP15[CP15_INVALIDATE_DATA_CACHE_LINE_USING_MVA] = value; + else if (opcode_2 == 2) + cpu->CP15[CP15_INVALIDATE_DATA_CACHE_LINE_USING_INDEX] = value; + } + else if (crm == 7 && opcode_2 == 0) + { + cpu->CP15[CP15_INVALIDATE_DATA_AND_INSTR_CACHE] = value; + } + else if (crm == 10) + { + if (opcode_2 == 0) + cpu->CP15[CP15_CLEAN_DATA_CACHE] = value; + else if (opcode_2 == 1) + cpu->CP15[CP15_CLEAN_DATA_CACHE_LINE_USING_MVA] = value; + else if (opcode_2 == 2) + cpu->CP15[CP15_CLEAN_DATA_CACHE_LINE_USING_INDEX] = value; + } + else if (crm == 14) + { + if (opcode_2 == 0) + cpu->CP15[CP15_CLEAN_AND_INVALIDATE_DATA_CACHE] = value; + else if (opcode_2 == 1) + cpu->CP15[CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_MVA] = value; + else if (opcode_2 == 2) + cpu->CP15[CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_INDEX] = value; + } + } + else if (crn == 8 && opcode_1 == 0) + { + LOG_WARNING(Core_ARM11, "TLB operations not fully implemented."); + + if (crm == 5) + { + if (opcode_2 == 0) + cpu->CP15[CP15_INVALIDATE_ITLB] = value; + else if (opcode_2 == 1) + cpu->CP15[CP15_INVALIDATE_ITLB_SINGLE_ENTRY] = value; + else if (opcode_2 == 2) + cpu->CP15[CP15_INVALIDATE_ITLB_ENTRY_ON_ASID_MATCH] = value; + else if (opcode_2 == 3) + cpu->CP15[CP15_INVALIDATE_ITLB_ENTRY_ON_MVA] = value; + } + else if (crm == 6) + { + if (opcode_2 == 0) + cpu->CP15[CP15_INVALIDATE_DTLB] = value; + else if (opcode_2 == 1) + cpu->CP15[CP15_INVALIDATE_DTLB_SINGLE_ENTRY] = value; + else if (opcode_2 == 2) + cpu->CP15[CP15_INVALIDATE_DTLB_ENTRY_ON_ASID_MATCH] = value; + else if (opcode_2 == 3) + cpu->CP15[CP15_INVALIDATE_DTLB_ENTRY_ON_MVA] = value; + } + else if (crm == 7) + { + if (opcode_2 == 0) + cpu->CP15[CP15_INVALIDATE_UTLB] = value; + else if (opcode_2 == 1) + cpu->CP15[CP15_INVALIDATE_UTLB_SINGLE_ENTRY] = value; + else if (opcode_2 == 2) + cpu->CP15[CP15_INVALIDATE_UTLB_ENTRY_ON_ASID_MATCH] = value; + else if (opcode_2 == 3) + cpu->CP15[CP15_INVALIDATE_UTLB_ENTRY_ON_MVA] = value; + } + } + else if (crn == 9 && opcode_1 == 0 && crm == 0 && opcode_2 == 0) + { + cpu->CP15[CP15_DATA_CACHE_LOCKDOWN] = value; + } + else if (crn == 10 && opcode_1 == 0) + { + if (crm == 0 && opcode_2 == 0) + { + cpu->CP15[CP15_TLB_LOCKDOWN] = value; + } + else if (crm == 2) + { + if (opcode_2 == 0) + cpu->CP15[CP15_PRIMARY_REGION_REMAP] = value; + else if (opcode_2 == 1) + cpu->CP15[CP15_NORMAL_REGION_REMAP] = value; + } + } + else if (crn == 13 && opcode_1 == 0 && crm == 0) + { + if (opcode_2 == 0) + cpu->CP15[CP15_PID] = value; + else if (opcode_2 == 1) + cpu->CP15[CP15_CONTEXT_ID] = value; + else if (opcode_2 == 3) + cpu->CP15[CP15_THREAD_URO] = value; + else if (opcode_2 == 4) + cpu->CP15[CP15_THREAD_PRW] = value; + } + else if (crn == 15) + { + if (opcode_1 == 0 && crm == 12) + { + if (opcode_2 == 0) + cpu->CP15[CP15_PERFORMANCE_MONITOR_CONTROL] = value; + else if (opcode_2 == 1) + cpu->CP15[CP15_CYCLE_COUNTER] = value; + else if (opcode_2 == 2) + cpu->CP15[CP15_COUNT_0] = value; + else if (opcode_2 == 3) + cpu->CP15[CP15_COUNT_1] = value; + } + else if (opcode_1 == 5) + { + if (crm == 4) + { + if (opcode_2 == 2) + cpu->CP15[CP15_READ_MAIN_TLB_LOCKDOWN_ENTRY] = value; + else if (opcode_2 == 4) + cpu->CP15[CP15_WRITE_MAIN_TLB_LOCKDOWN_ENTRY] = value; + } + else if (crm == 5 && opcode_2 == 2) + { + cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS] = value; + } + else if (crm == 6 && opcode_2 == 2) + { + cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS] = value; + } + else if (crm == 7 && opcode_2 == 2) + { + cpu->CP15[CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE] = value; + } + } + else if (opcode_1 == 7 && crm == 1 && opcode_2 == 0) + { + cpu->CP15[CP15_TLB_DEBUG_CONTROL] = value; + } + } + } + + // Unprivileged registers + if (crn == 7 && opcode_1 == 0 && crm == 5 && opcode_2 == 4) + { + cpu->CP15[CP15_FLUSH_PREFETCH_BUFFER] = value; + } + else if (crn == 7 && opcode_1 == 0 && crm == 10) + { + if (opcode_2 == 4) + cpu->CP15[CP15_DATA_SYNC_BARRIER] = value; + else if (opcode_2 == 5) + cpu->CP15[CP15_DATA_MEMORY_BARRIER] = value; + + } + else if (crn == 13 && opcode_1 == 0 && crm == 0 && opcode_2 == 2) + { + cpu->CP15[CP15_THREAD_UPRW] = value; + } +} |