diff options
Diffstat (limited to 'src/core/arm/dyncom/arm_dyncom_dec.cpp')
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_dec.cpp | 28 |
1 files changed, 23 insertions, 5 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_dec.cpp b/src/core/arm/dyncom/arm_dyncom_dec.cpp index 12181d0e..3887189f 100644 --- a/src/core/arm/dyncom/arm_dyncom_dec.cpp +++ b/src/core/arm/dyncom/arm_dyncom_dec.cpp @@ -181,7 +181,11 @@ const ISEITEM arm_instruction[] = { { "ldrt", 3, 0, 26, 27, 0x00000001, 24, 24, 0x00000000, 20, 22, 0x00000003 }, { "mrc", 3, 6, 24, 27, 0x0000000e, 20, 20, 0x00000001, 4, 4, 0x00000001 }, { "mcr", 3, 0, 24, 27, 0x0000000e, 20, 20, 0x00000000, 4, 4, 0x00000001 }, - { "msr", 2, 0, 23, 27, 0x00000006, 20, 21, 0x00000002 }, + { "msr", 3, 0, 23, 27, 0x00000006, 20, 21, 0x00000002, 22, 22, 0x00000001 }, + { "msr", 4, 0, 23, 27, 0x00000006, 20, 21, 0x00000002, 22, 22, 0x00000000, 16, 19, 0x00000004 }, + { "msr", 5, 0, 23, 27, 0x00000006, 20, 21, 0x00000002, 22, 22, 0x00000000, 19, 19, 0x00000001, 16, 17, 0x00000000 }, + { "msr", 4, 0, 23, 27, 0x00000006, 20, 21, 0x00000002, 22, 22, 0x00000000, 16, 17, 0x00000001 }, + { "msr", 4, 0, 23, 27, 0x00000006, 20, 21, 0x00000002, 22, 22, 0x00000000, 17, 17, 0x00000001 }, { "ldrb", 3, 0, 26, 27, 0x00000001, 22, 22, 0x00000001, 20, 20, 0x00000001 }, { "strb", 3, 0, 26, 27, 0x00000001, 22, 22, 0x00000001, 20, 20, 0x00000000 }, { "ldr", 4, 0, 28, 31, 0x0000000e, 26, 27, 0x00000001, 22, 22, 0x00000000, 20, 20, 0x00000001 }, @@ -190,12 +194,17 @@ const ISEITEM arm_instruction[] = { { "cdp", 2, 0, 24, 27, 0x0000000e, 4, 4, 0x00000000 }, { "stc", 2, 0, 25, 27, 0x00000006, 20, 20, 0x00000000 }, { "ldc", 2, 0, 25, 27, 0x00000006, 20, 20, 0x00000001 }, - { "swi", 1, 0, 24, 27, 0x0000000f }, - { "bbl", 1, 0, 25, 27, 0x00000005 }, { "ldrexd", 2, ARMV6K, 20, 27, 0x0000001B, 4, 7, 0x00000009 }, { "strexd", 2, ARMV6K, 20, 27, 0x0000001A, 4, 7, 0x00000009 }, { "ldrexh", 2, ARMV6K, 20, 27, 0x0000001F, 4, 7, 0x00000009 }, { "strexh", 2, ARMV6K, 20, 27, 0x0000001E, 4, 7, 0x00000009 }, + { "nop", 5, ARMV6K, 23, 27, 0x00000006, 22, 22, 0x00000000, 20, 21, 0x00000002, 16, 19, 0x00000000, 0, 7, 0x00000000 }, + { "yield", 5, ARMV6K, 23, 27, 0x00000006, 22, 22, 0x00000000, 20, 21, 0x00000002, 16, 19, 0x00000000, 0, 7, 0x00000001 }, + { "wfe", 5, ARMV6K, 23, 27, 0x00000006, 22, 22, 0x00000000, 20, 21, 0x00000002, 16, 19, 0x00000000, 0, 7, 0x00000002 }, + { "wfi", 5, ARMV6K, 23, 27, 0x00000006, 22, 22, 0x00000000, 20, 21, 0x00000002, 16, 19, 0x00000000, 0, 7, 0x00000003 }, + { "sev", 5, ARMV6K, 23, 27, 0x00000006, 22, 22, 0x00000000, 20, 21, 0x00000002, 16, 19, 0x00000000, 0, 7, 0x00000004 }, + { "swi", 1, 0, 24, 27, 0x0000000f }, + { "bbl", 1, 0, 25, 27, 0x00000005 }, }; const ISEITEM arm_exclusion_code[] = { @@ -375,6 +384,10 @@ const ISEITEM arm_exclusion_code[] = { { "mrc", 0, 6, 0 }, { "mcr", 0, 0, 0 }, { "msr", 0, 0, 0 }, + { "msr", 0, 0, 0 }, + { "msr", 0, 0, 0 }, + { "msr", 0, 0, 0 }, + { "msr", 0, 0, 0 }, { "ldrb", 0, 0, 0 }, { "strb", 0, 0, 0 }, { "ldr", 0, 0, 0 }, @@ -383,12 +396,17 @@ const ISEITEM arm_exclusion_code[] = { { "cdp", 0, 0, 0 }, { "stc", 0, 0, 0 }, { "ldc", 0, 0, 0 }, - { "swi", 0, 0, 0 }, - { "bbl", 0, 0, 0 }, { "ldrexd", 0, ARMV6K, 0 }, { "strexd", 0, ARMV6K, 0 }, { "ldrexh", 0, ARMV6K, 0 }, { "strexh", 0, ARMV6K, 0 }, + { "nop", 0, ARMV6K, 0 }, + { "yield", 0, ARMV6K, 0 }, + { "wfe", 0, ARMV6K, 0 }, + { "wfi", 0, ARMV6K, 0 }, + { "sev", 0, ARMV6K, 0 }, + { "swi", 0, 0, 0 }, + { "bbl", 0, 0, 0 }, { "bl_1_thumb", 0, INVALID, 0 }, // Should be table[-4] { "bl_2_thumb", 0, INVALID, 0 }, // Should be located at the end of the table[-3] |