diff options
| author |  Lioncash <mathew1800@gmail.com> | 2015-05-13 17:29:59 -0400 |
|---|---|---|
| committer | Lioncash <mathew1800@gmail.com> | 2015-05-14 16:24:39 -0400 |
| commit | be0119be0816c3bb431e17916659453c1d25b4d8 (patch) | |
| tree | b3bab345e2d03f7e227e1fad1aae0f4863fec39e /src/core/arm/dyncom/arm_dyncom_interpreter.cpp | |
| parent | e83bc5b7ee45ae24821c4cd185dd6a14dbd3b4d4 (diff) | |
dyncom: Move exclusive load/stores above bbl and swi in the decoding table
Diffstat (limited to 'src/core/arm/dyncom/arm_dyncom_interpreter.cpp')
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_interpreter.cpp | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp index 8c52bdb7..8de46294 100644 --- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp +++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp @@ -3544,12 +3544,12 @@ const transop_fp_t arm_instruction_trans[] = { INTERPRETER_TRANSLATE(cdp), INTERPRETER_TRANSLATE(stc), INTERPRETER_TRANSLATE(ldc), - INTERPRETER_TRANSLATE(swi), - INTERPRETER_TRANSLATE(bbl), INTERPRETER_TRANSLATE(ldrexd), INTERPRETER_TRANSLATE(strexd), INTERPRETER_TRANSLATE(ldrexh), INTERPRETER_TRANSLATE(strexh), + INTERPRETER_TRANSLATE(swi), + INTERPRETER_TRANSLATE(bbl), // All the thumb instructions should be placed the end of table INTERPRETER_TRANSLATE(b_2_thumb), @@ -3920,12 +3920,12 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { case 180: goto CDP_INST; \ case 181: goto STC_INST; \ case 182: goto LDC_INST; \ - case 183: goto SWI_INST; \ - case 184: goto BBL_INST; \ - case 185: goto LDREXD_INST; \ - case 186: goto STREXD_INST; \ - case 187: goto LDREXH_INST; \ - case 188: goto STREXH_INST; \ + case 183: goto LDREXD_INST; \ + case 184: goto STREXD_INST; \ + case 185: goto LDREXH_INST; \ + case 186: goto STREXH_INST; \ + case 187: goto SWI_INST; \ + case 188: goto BBL_INST; \ case 189: goto B_2_THUMB ; \ case 190: goto B_COND_THUMB ; \ case 191: goto BL_1_THUMB ; \ @@ -3980,8 +3980,9 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { &&MLA_INST,&&SSAT_INST,&&USAT_INST,&&MRS_INST,&&MSR_INST,&&AND_INST,&&BIC_INST,&&LDM_INST,&&EOR_INST,&&ADD_INST,&&RSB_INST,&&RSC_INST, &&SBC_INST,&&ADC_INST,&&SUB_INST,&&ORR_INST,&&MVN_INST,&&MOV_INST,&&STM_INST,&&LDM_INST,&&LDRSH_INST,&&STM_INST,&&LDM_INST,&&LDRSB_INST, &&STRD_INST,&&LDRH_INST,&&STRH_INST,&&LDRD_INST,&&STRT_INST,&&STRBT_INST,&&LDRBT_INST,&&LDRT_INST,&&MRC_INST,&&MCR_INST,&&MSR_INST, - &&LDRB_INST,&&STRB_INST,&&LDR_INST,&&LDRCOND_INST, &&STR_INST,&&CDP_INST,&&STC_INST,&&LDC_INST,&&SWI_INST,&&BBL_INST,&&LDREXD_INST, - &&STREXD_INST,&&LDREXH_INST,&&STREXH_INST,&&B_2_THUMB, &&B_COND_THUMB,&&BL_1_THUMB, &&BL_2_THUMB, &&BLX_1_THUMB, &&DISPATCH, + &&LDRB_INST,&&STRB_INST,&&LDR_INST,&&LDRCOND_INST, &&STR_INST,&&CDP_INST,&&STC_INST,&&LDC_INST, &&LDREXD_INST, + &&STREXD_INST,&&LDREXH_INST,&&STREXH_INST, &&SWI_INST,&&BBL_INST, + &&B_2_THUMB, &&B_COND_THUMB,&&BL_1_THUMB, &&BL_2_THUMB, &&BLX_1_THUMB, &&DISPATCH, &&INIT_INST_LENGTH,&&END }; #endif |