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author | Lioncash <mathew1800@gmail.com> | 2015-07-29 04:13:46 -0400 |
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committer | Lioncash <mathew1800@gmail.com> | 2015-07-29 10:57:47 -0400 |
commit | 2e420aba3c007bff84988cf1c281db73c12c7f9a (patch) | |
tree | 039f0d852266d40de51982330d04aa54b68b8cef /src/core/arm/dyncom/arm_dyncom_interpreter.cpp | |
parent | 7c7eeb9d34c84ede941a394195bac34c9a4813fd (diff) |
dyncom: Handle the case where PC is the source register for STR/VSTM/VLDM
Diffstat (limited to 'src/core/arm/dyncom/arm_dyncom_interpreter.cpp')
-rw-r--r-- | src/core/arm/dyncom/arm_dyncom_interpreter.cpp | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp index 0c20c2bc..759ef728 100644 --- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp +++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp @@ -5997,7 +5997,12 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { ldst_inst* inst_cream = (ldst_inst*)inst_base->component; inst_cream->get_addr(cpu, inst_cream->inst, addr); - unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)]; + unsigned int reg = BITS(inst_cream->inst, 12, 15); + unsigned int value = cpu->Reg[reg]; + + if (reg == 15) + value += 2 * cpu->GetInstructionSize(); + cpu->WriteMemory32(addr, value); } cpu->Reg[15] += cpu->GetInstructionSize(); |