From 70e06336786ce23b7702f8a48d31b3cfa09e75fd Mon Sep 17 00:00:00 2001 From: Benjamin Barenblat Date: Fri, 27 Feb 2015 21:14:48 -0500 Subject: Initial commit --- README.md | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 README.md (limited to 'README.md') diff --git a/README.md b/README.md new file mode 100644 index 0000000..a5f6b02 --- /dev/null +++ b/README.md @@ -0,0 +1,25 @@ +# Bluespec buffer bank + +This is a synthesizable 8-element buffer bank written in Bluespec SystemVerilog +(BSV). It’s a reasonable Bluespec ‘hello world’ example. + +The included constraints file targets the [Digilent Nexys4] development board, +but you should be able to easily modify it to work with any FPGA. + +## Licence + +This program is free software: you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free Software +Foundation, either version 3 of the License, or (at your option) any later +version. + +This program is distributed in the hope that it will be useful, but **without +any warranty**; without even the implied warranty of **merchantability** or +**fitness for a particular purpose**. See the GNU General Public License for +more details. + +You should have received a copy of the GNU General Public License along with +this program. If not, see . + + +[Digilent Nexys4]: http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS4 -- cgit v1.2.3